Pierre Maillard

Neutron, 64 MeV Proton, Thermal Neutron and Alpha Single-Event Upset Characterization of Xilinx 20nm UltraScale Kintex FPGA

The single-event response of Xilinx 20nm UltraScale Kintex FPGA is characterized using neutron, 64 MeV proton, thermal neutron and alpha foil irradiation sources. Single-event upset and multi-bits upset results are presented.

Impact of Temperature and Vcc Variation on 20nm Kintex UltraScale FPGAs Neutron Soft Error Rate

The single-event response vs. temperature and Vcc supply voltage of the 20nm Kintex UltraScale FPGA is characterized using a 64 MeV proton beam as proxy for atmospheric neutron. Single-event upset and multi-bit upset results are presented.

64 MeV proton single-event upset characterization of customer memory interface design on Xilinx XCKU040 FPGA

This paper examines the single-event upset response of a customer memory interface design on the Xilinx 20nm XCKU040 Field Programmable Gate Array (FPGA) irradiated with 64MeV proton source. Results for single-event upsets on configuration RAM (CRAM) cells are provided. The difference between architectural vulnerability factor (AVF) and design vulnerability factor (DVF) of the customer memory interface design is also discussed in this work.

Neutron, 64 MeV proton & alpha single-event characterization of Xilinx 16nm FinFET Zynq® UltraScale+™ MPSoC

This paper examines the single-event effect response of the Xilinx 16nm FinFET XCZU9EG Zynq® MPSoC irradiated with neutrons, 64 MeV protons and thermal neutrons sources. A 16nm FPGA-like test chip was also built for alpha foil testing. Results for single-event upsets on configuration RAM (CRAM) cells and block RAM (bRAM) cells are provided for the programmable logic. In addition, the 1st· Xilinx 16nm FinFET processor (PS) SEE results are also presented.