Avi Kornblit

Inverted thin-film transistors with a simple self-aligned lightly doped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L/sub ch/. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L/sub ch/, L/sub LDD/, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of approximately 1.25 mu A at 5 V and a leakage current of approximately 0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is approximately 7*10/sup 6/. >

Reactive ion etching profile and depth characterization using statistical and neural network analysis of light scattering data

As device design rules continue to shrink for the manufacturing of integrated circuits, unprecedented challenges for process inspection appear. No longer is optical microscopy adequate for determining if process results meet specifications. On the other hand, the alternative—scanning electron microscopy—is time consuming, destructive, and costly. Another approach is to measure scattered light intensity as a function of scattering angle, as opposed to imaging, to obtain distinct signatures for submicron structures. In this work, a set of Si wafers with photolithographically defined lines and spaces are reactively ion etched. By varying process conditions, a range of depths and sidewall profiles is generated and then inspected by detecting visible scattered laser light over 180°. The resultant scattergrams are then analyzed both by using discriminant analysis and by training a neural network to catalog the microstructures according to depth and profile. We find that this approach is a viable alternative to ...

Sub-0.1 μm NMOS transistors fabricated using laser-plasma point-source X-ray lithography

We report the experimental results of the first MOSFETs ever fabricated using a laser plasma-source X-ray stepper. The minimum gate length of these transistors is 0.12 /spl mu/m with an effective channel length of 0.075 /spl mu/m. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source X-ray stepper while the other layers were patterned using optical lithography.<<ETX>>

Laser scatterometry for process characterization

Abstract : Laser scatterometry is a technique which involves shining a light beam on an area to be characterized and measuring the angular distribution of the light that is scattered from that area. A laser is used so that the incident light will be monochromatic and coherent. It is also valuable, in many applications, to be able to confine the probe beam to a selected area, with a diameter of 10 um or more. The scattered light distribution is typically measured either by scanning a detector over an arc, using a fixed array of photodiodes that are mounted along an arc, or by measuring the scattered light intensity distribution at a hemispherical screen when sample symmetry requires more than a one dimensional distribution measurement. In most cases, a single line measurement along a 90 deg arc is sufficient, either because of sample symmetry or because of the ability to align the sample in the direction of interest. The wavelength of the light used is a determining factor in the range of feature sizes that will be measured. Thus, different wavelength sources are sometimes valuable. Also, the angle of incidence of the probing light beam is a factor in the range of features that will be characterized.

Analyzing simulated and measured optical scatter for semiconductor process verification

We describe an experiment in which the etch depth of a diffraction grating is measured. A simulated experiment is used to develop and calibrate the measurement technique. A scatterometer was used to measure the diffraction patterns of a set of 5 wafers at 14 die locations. The estimator already developed is then used to find the etch depths at the 70 measured locations. Finally, a scanning force microscope is used as a reference method to validate the scatterometer measurements.

Linewidth Control In Trilevel Etching

In a trilevel resist system, the thick polymer planarizing layer serves as the masking layer for pattern transfer to the substrate. This paper addresses the problems of achieving accurate pattern transfer to the planarizing layer. As in every Reactive Ion Etch (RIE) step, linewidth changes should be minimized in order to achieve faithful representation of the lithographic pattern. Linewidth loss can take place during the pattern transfer to the intermediate layer because of excessive resist erosion, due to erosion of the intermediate layer during pattern transfer to the planarizing layer, and due to lateral etch of the planarizing layer during its definition. As critical dimensions decrease below 1 tan and device density increases, proximity may affect line shape and width too. Methods to minimize linewidth changes due to the above mechanisms are discussed; specifically, the advantages of using carbon-dioxide for the planarizing layer etch are presented.

Device fabrication and characteristics of surface-channel PMOSFET with WSi/sub x/ polycide gate using dopant drive-out technique

Surface-channel PMOSFETs have been realized using a dopant-drive-out technique with WSi/sub x/ polycide gate. The advantages of this technique include (1) excellent thermal stability, (2) superior electrical device characteristics suitable for deep sub-half micron technology, (3) 10 Omega / Square Operator sheet resistance for a thin gate stack (<or=200 nm), (4) less severe gate topography, and (5) suppression of ion-penetration effects during gate implantation.<<ETX>>

Sub-0.1-μm NMOS transistors fabricated using point-source x-ray lithography

As transistor features shrink into the deep submicron range, a corresponding reduction in the optical wavelength used to pattern such features has also continued. Currently, advanced optical steppers found in ULSI production applications operate at a wavelength of 365 nm with 248 nm optical lithography present in process development facilities and 193 nm lithography in the early stages of research. By reducing the wavelength still further to below 1.5 nm, x-ray lithography represents the ultimate limit of this paradigm. In this paper we present the experimental results of the first MOSFETs ever fabricated using a laser plasma-source x-ray stepper. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source x-ray stepper while the other layers were patterned using an optical stepper operating at a wavelength of 248 nm (DUV). The minimum gate length of these transistors is 0.12 micrometers with an effective channel length of 75 nm.

Etching-related reverse short channel effect in buried channel P-MOSFET

We have studied the effects of gate etching on the threshold voltage of submicron, N-poly gate CMOS devices through etch processing in selected advanced commercial etchers using a variety of etching chemistries. We found that the threshold voltage of the P-channel (buried channel) transistors is very sensitive to the etched profile of the gate. In the cases of reentrant and/or notched profiles, a reverse short channel phenomenon was observed. However, the etched profile has little effect on the threshold voltage of the N-channel transistors. A model is proposed to explain the mechanism of the reverse short channel phenomenon. Cross-sectional SEM and electrical measurements are used to support the model. The impact of this reverse short channel phenomenon on manufacturability and reliability for buried channel devices is also discussed.