Peter Kämmerling

New synchronisation system for experiments at COSY

To improve existing experiments at COSY a new DAQ system is currently under development. It is also well suited to the requirements of WASA at COSY after its transfer from CELSIUS. The DAQ modules are scattered to about 10..20 crates and are able to digitize and store several thousands events before a computer engagement is required. Therefore we need a purely hardware based synchronisation system. The synchronisation system consists of one master module and several output modules housed in a proprietary LVDS crate. It communicates over point to point links with the crate controllers

The high-intensity reflectometer of the Jülich Centre for Neutron Science: MARIA

MARIA is a world class vertical sample reflectometer dedicated to the investigation of thin films in the fields of magnetism, soft matter and biology. With the elliptical vertically focusing guide and a wavelength resolution of Δλ/λ = 10%, the non-polarized flux at the sample position amounts to 1.2 × 108 n (s cm2)−1. Besides the polarized and non-polarized reflectivity mode for specular and off-specular reflectivity measurements, MARIA can also be used to carry out grazing-incidence small-angle neutron scattering investigations.

Development of an AMC Module Management Controller

Most functional devices of an ATCA crate contain a controller to handle the management. We designed an AMC board and used a PIC32 for the MMC. Together with the gcc toolchain we chose an open source code as starting point.

IPMI test software for MicroTCA developments

To support our MicroTCA (AMC) module developments, and for diagnostic investigations in MicroTCA systems, we found a need to develop tools to exercise the IPMI functions of Management Controllers within the system. Based on the freely available ”ipmitool” program, we built a framework which allows to communicate with AMC Module Management Controllers through the Shelf Managers network interface, without need to tap an IPMB. It contains functions to exercise various IPMI transactions and to check integrity and correctness of FRU (Field Replacable Unit) information and other data structures published by Management Controllers. The general structure of the library will be presented, as well as first results and future plans.

Developments for the readout of the PANDA micro vertex detector

The experiment PANDA (Antiproton Annihilation at Darmstadt) is under development for the future accelerator facility FAIR in Darmstadt, Germany. In the target spectrometer of PANDA a micro-vertex detector (MVD) will be used as the central tracking detector for charged particles. The design of the MVD is based on silicon strip detectors at the outer layer and on silicon pixel detectors at the inner layers. The paper discusses the requirements and first concepts of the DAQ system for the MVD which has to be finished about 2015. It presents the design of the lab system that has been developed already now for the test and readout of different frontend chips for pixel detectors. The lab system consists of a flexible readout board coupled via the SIS1100 Gigabit link to PCI. A further improvement of the lab system employing a 2 Gbit/s optical link to PCIe is introduced.

MicroTCA developments for PANDA data acquisition

For data acquisition frontend developments as ADCs, TDCs and custom logics, we are moving to MicroTCA based systems.

MicroTCA at the Multiplexing Level in the readout of the PANDA micro vertex detector

The PANDA (AntiProton Annihilation at Darmstadt) detector system is under development for the future accelerator facility FAIR in Darmstadt, Germany. In the target spectrometer of PANDA a micro-vertex detector (MVD) will be used as the central tracking detector for charged particles. The design of the MVD is based on silicon strip detectors at the outer layer and on silicon pixel detectors at the inner layers. Data from the readout ASICs in the front end are sent via GBT opical link (CERN development) to a Multiplexing Layer, where 3 GBT links are aggregated to 1 10 Gbit/s optical link to the Level-1 Trigger network. The Multiplexing Layer will be implemented with MTCA.4. The so-called HGF-AMC, a versatile AMC module developed by DESY in cooperation with KIT, will be used for the aggregation of the GBT links. The HGF-AMC is based on a Kintex-7 FPGA and supports MTCA.4.

Design of an optical uplink with 10 GBit/s between PCIe and MicroTCA

In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.

Development of a high resolution TDC module for MicroTCA based on the GPX ASIC

A high resolution time to digital conversion (TDC) module has been developed for the readout of drift tubes in the PANDA detector system planned at the future FAIR facility in Darmstadt, Germany. The board is designed as a double width compact size MicroTCA module. The backplane communication is based on PCI Express according to AMC.1. PCI Express is implemented with a Xilinx XC5VLX30T FPGA using an embedded PCI Express Endpoint Block and 4 Rocket IO GTP Transceivers. The Module Management Controller (MMC) is implemented with a Microchip PIC32MX460F512L microcontroller with integrated I2C interfaces. The TDC module provides 32 channels and is based on the GPX ASIC from acammesselectronic gmbh. In the selected mode the GPX has 8 input channels with a resolution up to 81 ps.

FPGA Configuration by TCP/IP and Ethernet

A RAM based FPGA can be configured with a bootimage from a local proprietary flash prom, by a JTAG adapter hooked to a local PC interface or any another component, which copes with one of the FPGA configuration protocols. The development of the FPGA code as well as updates of the bootimage can be done by a JTAG adapter. On the basis of a PCB developed in the ZEL we show a first step towards an embedded JTAG adapter for TCP/IP-Ethernet.