Aydin I. Karsilayan

Energy harvesting using martensite variant reorientation mechanism in a NiMnGa magnetic shape memory alloy

Magnetic shape memory alloys demonstrate significant potential for harvesting waste mechanical energy utilizing the Villari effect. In this study, a few milliwatts of power output are achieved taking advantage of martensite variant reorientation mechanism in Ni51.1Mn24Ga24.9 single crystals under slowly fluctuating loads (10Hz) without optimization in the power conversion unit. Effects of applied strain range, bias magnetic field, and loading frequency on the voltage output are revealed. Anticipated power outputs under moderate frequencies are predicted showing that the power outputs higher than 1W are feasible.

Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching

An ultrahigh-speed fully differential charge pump with minimum current mismatch and variation is proposed in this brief. A mismatch suppression circuit is employed to minimize the mismatch between the charging and discharging currents, which minimizes the steady-state phase error in a phase-locked loop (PLL). A variation suppression circuit is proposed to minimize output current variation with the change of output voltage, which reduces the variation of the bandwidth in a PLL. Techniques are proposed to suppress both low-speed glitches and high-speed glitches in the output current to allow glitch-free operation of the charge pump with ultrafast input pulses. The differential charge pump is designed and simulated under the power supply of 3.3 V in TSMC 0.35-mum CMOS technology to verify the effectiveness of the proposed techniques

An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA-based bandpass filter

A tuning scheme for continuous-time high-Q biquad filters is presented. An improvement over the existing implementation of the modified-LMS Q-tuning scheme is proposed and efficiently combined with the frequency tuning based on phase-locked loops. The proposed scheme takes much less area without compromising the accuracy achieved previously. The proposed unified Q- and f/sub 0/-tuning scheme does not require the Q-tuning loop to be slower than the f/sub 0/-tuning loop. The optimal case is to have equal speeds for both loops. Also, a low-voltage pseudo-differential operational transconductance amplifier with inherent common-mode feedforward is introduced. The structure is fully symmetric and suitable for high-frequency applications. An experimental test chip is fabricated in standard CMOS 0.5-/spl mu/m technology, with a bandpass filter of center frequency 100 MHz and Q of 20, along with the proposed tuning scheme. The measured Q-tuning error is around 1%. Expected and experimental results are in good agreement.

A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz

A low power divide-by-8 injection-locked frequency divider is presented. The frequency divider consists of four current-mode logic (CML) D-latches connected in the form of a four-stage ring with the differential input signal injected into the clock terminals of the latches. The output signals can be taken from the data terminals of any of the four latches. The proposed frequency divider has higher operating frequency and lower power dissipation compared with conventional static frequency dividers. Compared with existing injection-locked frequency dividers, the proposed fully differential frequency divider presents wider locking range with the center frequency independent of injection amplitude. The frequency divider is implemented in TSMC 0.18 mum CMOS technology. It consumes around 3.6 mW power with 1.8 V supply. The operating frequency can be tuned from 4 GHz to 18 GHz. The ratio of the locking range over the center frequency is up to 50% depending on the operating frequency and biasing conditions.

A rail-to-rail amplifier input stage with /spl plusmn/0.35%g/sub m/ fluctuation

A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant g/sub m/ is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5-/spl mu/m process. The resulting differential pair had a constant transconductance that varied by only /spl plusmn/0.35% for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of /spl plusmn/1.5V, resulting in only /spl plusmn/1% fluctuation in g/sub m/ for input common modes from -2 to 2 V.

Self-Powered Rectifier for Energy Harvesting Applications

In this paper, a self-powered rectifier is proposed with an intended application in energy harvesting systems and wireless sensor networks. Key points in the design of the rectifier are discussed as well as practical limitations of the circuit. The proposed self-powered rectifier was designed and fabricated in a standard 0.5-μm complementary metal-oxide-semiconductor process using standard components and poly-poly capacitors. Measurement results are presented for single and four-stage rectifiers with resistive loads from 10 kΩ to 10 MΩ and sinusoidal input amplitudes from 100-1000 mVpk. For the specified input and loading conditions, the maximum measured output voltages for the proposed single stage and four-stage rectifiers were 0.8 and 3.5 V, respectively.

Low-Power Circuits and Energy Harvesting for Structural Health Monitoring of Bridges

In this paper, we present a self-powered wireless sensor system for structural health monitoring of highway bridges. The system consists of an energy harvesting material, power conditioning circuitry, a sensor, an analog-to-digital converter, and a wireless transmitter. The energy harvesting material is a recently discovered NiMnCoIn magnetic shape memory alloy (MSMA), which converts mechanical vibrations first into a magnetization change and then, with assistance from a pick-up coil, into an alternating current (ac) output. The ac output of the MSMA is converted to a direct current (dc) voltage for powering a sensor and circuitry. Measurement results from a self-powered rectifier (SPR) and a six-bit successive approximation register analog-to-digital converter (SAR ADC) are presented, and implementation considerations are presented for the sensor and wireless transmitter. The SPR produces dc output voltages larger than 700 mV for loads larger than 100 kΩ with peak input amplitudes >;400 mVpk. A four-stage rectifier-multiplier is also implemented utilizing the proposed SPR as the first stage. The implemented SAR ADC is functional with a 0.9-V dc supply voltage (Vdd) and achieves an improved performance with a Vdd of 1.8 V, where the SAR ADC achieves a measured integral nonlinearity and differential nonlinearity of +1.2/-1.9 least significant bit and +1.3/-0.99 LSB, respectively. The SPR and SAR ADC are fabricated in a standard 0.5-μm CMOS process. The proposed sensor system can be fully optimized due to co-design capabilities. The lack of batteries makes this system ideal for deployment in bridge monitoring systems.

A digital automatic tuning technique for high-order continuous-time filters

A digital automatic tuning technique for high-order continuous-time filters is proposed. Direct tuning of overall response is achieved without separating individual biquad sections, eliminating switches and their parasitics. Output phase of each biquad section is tuned to known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase detection. Frequency and quality factor tuning loops for each biquad are controlled digitally, providing more stable tuning by activating only one loop at a given time. The tuning system was verified by a prototype sixth-order bandpass filter which was fabricated in a conventional 0.5 /spl mu/m CMOS process with /spl plusmn/1.5 V power supply.

Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector

Phase-locked loops (PLLs) using binary phase detectors (BPDs) are modeled and analyzed in this paper. Steady-state behavior for PLLs based on BPDs (BPLs) using first- and second- order loop filters is characterized using transient waveform equations. It is shown that BPLL has a range of oscillation modes in steady state when there is no input jitter. The BPLL is most likely to operate at the most stable oscillation mode (MSOM) under the disturbance of random input jitter. The MSOM is determined by evaluating the relative stability of all the modes. The expected value of the output jitter amplitude is derived and its dependence on the loop parameters is analyzed.

An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation

A phase shift technique using capacitive source degeneration (CSD) is presented for LC quadrature voltage-controlled oscillators (QVCO), where capacitively degenerated differential pairs are used to couple the LC tanks to implement a phase-shifted transconductance and negative input resistance to compensate resonator losses, and to minimize the flicker noise contributions. The CSD technique not only introduces excess phase shift to eliminate undesired bi-modal oscillation, but inherently provides a large coupling ratio to improve quadrature phase accuracy. Compared to existing phase-shift LC-QVCOs, the proposed CSD-QVCO presents excellent phase accuracy and power efficiency. A prototype of the QVCO was fabricated in TSMC 0.18-μm CMOS technology. The measured phase noise is -120 dBc/Hz at 3-MHz offset from 5-GHz carrier, with a power consumption of 6.4 mW from a 1.2-V supply.