Hemasundar Mohan Geddada

Wide-Band Inductorless Low-Noise Transconductance Amplifiers With High Large-Signal Linearity

Two high-linearity inductorless broadband low-noise transconductance amplifiers (LNTAs) employing noise and distortion cancellation techniques are presented. The core design employs a common-gate input stage and a common-source error-amplifier (EA) stage. Stacked PMOS-NMOS topology enables large-signal operation while the drain current is reused. The high linearity performance is achieved by the derivative superposition of the pMOS and nMOS transistors that reduce the third-order distortion due to second-order interaction between input stage and EA stage. Critical design issues are carefully investigated along with the performance tradeoffs. In the fully differential architecture, the first LNTA covers 0.1-2-GHz bandwidth and achieves a minimum noise figure (NF) of 3 dB, third-order input intercept point (IIP3) of 10 dBm, and a 1-dB compression point of 0 dBm while dissipating 30.2 mW of dc power. The second lower power LNTA with bulk-driven technique achieves a minimum NF of 3.4 dB, IIP3 of 11 dBm, 0.1-3-GHz bandwidth at 16 mW of power consumption. Each LNTA occupies an active area of 0.06 mm2 in 45-nm CMOS.

26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS

The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (~5GS/s), mid-resolution (~10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive in terms of power efficiency and complexity compared to TI-pipelined ADCs [4], where the critical SNR, THD, and TI matching are only required in the MDACs resolving the MSBs. In this paper we report a hybrid of TI-pipelined MDAC and TI-SAR, in which the former resolves the 2 MSB bits and the latter resolves the 8 lower bits. This hybrid architecture combines the advantages from each ADC type to achieve better power at 5GS/s. The front-end is implemented by time-interleaving two 2.5b MDAC slices, easing the timing-matching requirement and complexity. The MDAC stage also eases the timing-matching requirement among the TI-SARs by presenting an amplified-and-held signal to each SAR input. This allows taking advantage of a low-resolution SARs simplicity and low power, for the last 8b. This work also proposes a SHA-less front-end to further minimize the ADC power. Two simple calibration techniques are introduced on-chip to enable the topology: (a) an over-range calibration (ORcal) loop to correct the sampling-time error between MDAC and sub-ADC in the SHA-less front-end, and (b) SAR reference calibration to align the SARs full-scale to the MDACs. Figure 26.6.1 shows the timing and functional block diagram of the 5GS/s hybrid SHA-less ADC. The RF buffer directly drives two TI-slices, each comprising a 2.5GS/S MDAC stage to resolve the 2.5 MSB bits, followed by 4-way interleaved 625MS/S SARs to resolve the lower 8b, for a combined 10b resolution (1b overlap), at 5GS/s.

Design Techniques to Improve Blocker Tolerance of Continuous-Time

Design techniques to provide robustness against loop saturation due to blockers in ΣA modulators are presented. Loop overload detection and correction are employed to improve the analog-to-digital converters (ADCs) tolerance to strong blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADCs blocker tolerance, a minimally invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. Measurement results show that the proposed ADC implemented in a 90nm CMOS process achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500 MHz and 17.1 mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5 dBFS while the conventional feedforward modulator becomes unstable at -23.5 dBFS of blocker power. The proposed blocker rejection techniques are minimally invasive and take less than 0.3 μs to settle after a strong agile blocker appears.

\Delta\Sigma

A 3-bit current-mode flash quantizer with current summing stage in a commercial 90-nm CMOS technology is presented. The topology is intended for low-power feed-forward continuous-time sigma-delta modulators. Current summation is realized using a common-gate structure. Replicas of the input signal current are compared with the reference currents through high-impedance nodes that ease the signal quantization. The comparison stage employs reset switches to enable fast comparisons. The proposed approach involves zero crossing comparators, and it employs current references instead of voltage references that demand a power-hungry resistive ladder. Results show that the proposed current-mode approach is faster than the conventional voltage-mode flash approach, and it requires a smaller input capacitance while consuming 53% less power. A 3-bit prototype design has a measured effective number of bits over 2.6 bits up to 2-GHz clock frequency with 10-MHz full-scale input signal. At 1.48-GHz clock frequency, the static differential nonlinearity (DNL) and integral nonlinearity (INL) errors are within -0.206 least significant bit (LSB) and 0.206 LSB, respectively. The proposed current-mode flash analog-to-digital converter (ADC) core dissipates 3.34-mW analog power from a 1.2 V supply while operating at 1.48 GHz. The core area of the ADC including the biasing circuitry is 0.0276 mm2.

ADCs

This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-approximation register (SAR). This architecture combines the benefits of both ADC topologies and allows significant power and complexity reduction. The high-speed 2.5 b MDAC front-end simplifies the complexity of time-interleaving (TI) and provides gain for attenuating the 8 b SAR non-idealities, when referred to the ADC input, relaxing its specifications and design. To further reduce power, the 2.5 b MDAC front-end is SHA-less, and an over-range calibration loop that allows operation at multi-GHz input is introduced. A calibration technique is also proposed to align the MDAC and SAR references, whose misalignment would otherwise produce integral non-linearity (INL) degradation. The ADC achieves -61.8 dB THD, 57.1 dB SNR for a 500 MHz input, while for a 2.35 GHz input it achieves -54.7 dB THD, 46.8 dB SNR (55.8 dB SNR excluding the integrated PLL contribution). The time-interleaving spur is 70 dBc. The ADC consumes 150 mW and occupies less than 0.5 mm2.

Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma–Delta Modulators

This paper presents a robust derivative superposition technique to improve the linearity performance of wideband low noise amplifiers (LNA). The technique is validated with two LNA designs in 0.18µm CMOS technology, by improving the IIP3 of a single-ended resistive terminated LNA by more than 10dB. Measurement results from 5 dies show that the proposed method improves IM3 over 20dB for input power up to −18dBm. A 2V inductorless broadband 0.3 to 2.8 GHz balun LNA with an active area of 0.06 mm2 was designed and measured. It achieves noise figure of 6.5dB, IIP3 of 16.8dBm, and P1dB of 0.5dBm having a power consumption of 14.2mW. The robustness of the technique to process variations is also discussed and validated.

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

This paper presents two linear broadband inductorless Low Noise Transconductance Amplifiers (LNTA) featuring high linearities for large signal (P1dB) and small signal (IIP3). The LNTAs utilize the complementary characteristics of NMOS and PMOS transistors to enhance the linearity. First prototype is a fully balanced current reuse LNTA achieving 0.12GHz bandwidth, minimum NF of 3dB, IIP3 of 10.8dBm and P1dB of 0dBm while dissipating 35mW. Second prototype proposes a low power bulk driven LNTA with 20mW of power consumption achieving comparable performances. Each LNTA occupy 0.06mm2 in 45nm CMOS.

Inductorless wideband CMOS LNAs with nonlinearity cancellation

A current-mode flash analog-to-digital converter (ADC) with current summing stage was designed and evaluated. The topology is intended for low-power feed-forward continuous-time sigma delta (CTSD) modulators and was fabricated in a commercial 90nm CMOS technology. A 3-bit prototype has an effective number of bits (ENOB) of 2.87 bits at 2GS/s with 12MHz full-range input power. The static DNL and INL errors are both in the range of 0.24 LSB. The ADC achieves an SNDR of 15dB with a 1GHz input signal and an SNDR above 19dB for input signals below 300MHz. A major advantage of this architecture is its voltage scalability as well as the reduced input capacitance. The proposed ADC core dissipates 3.1mW power from a 1.2V supply while operating at 2GHz.

Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS

A continuous-time low-pass ΔΣ ADC equipped with design techniques to provide robustness against saturation due to blockers is presented. An integrated low pass blocker filter that reduces the most critical adjacent/alternate channel blockers by 7/11 dB, respectively is implemented at the input of the ADC. The blocker filter is power efficient, highly linear and its noise is shaped out of signal band. Measurement results show that the proposed ADC implemented in a 90-nm digital CMOS process achieves 69 dB dynamic range over a 20 MHz bandwidth with a sampling frequency of 500 MHz and 17.1 mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is -12.5 dBFS in the presence of a -12 dBFS in-band signal while the conventional modulator becomes unstable for -23.5 dBFS blocker power. The proposed integrated blocker filter is non-invasive, low power (1.4mW) and does not degrade the stability of the ΔΣ loop.

A current-mode flash ADC for low-power continuous-time sigma delta modulators

Blocker and jitter sensitivity of continuous-time sigma-delta (CT-ΣΔ) converters is discussed. The interaction between blockers and clock jitter and its effect on the ADC resolution is also investigated. It is observed that out-of-band (OOB) blockers and clock jitter in the feedback DAC degrade the ADC resolution by convolving with the OOB quantization noise, thereby increasing the in-band noise floor. Some techniques on how to improve the blocker and jitter tolerance of CT-ΣΔ ADCs are outlined. It is verified that increased blocker tolerance relaxes the baseband channel filtering requirements in the signal path of a broadband receiver. By monitoring the internal signals of the ADC and dynamically controlling a front-end programmable gain amplifier, saturation and overload is avoided in the presence of strong interferers. The proposed blocker mitigation technique avoids changing the ADC internal loop parameters dynamically, resulting in fast settling time performance with moderate penalties in SNDR and circuit complexity.