Ayhan A. Mutlu

Concurrent optimization of process dependent variations in different circuit performance measures

A method for multi-objective circuit variability optimization in the presence of process variations is presented. Critical process parameter variations are identified by determining their correlations to the circuit performance measures of interest. Then, the distributions of these critical process parameters are used to identify the critical designable parameters for variability optimization. Membership functions and fuzzy set intersection operators are used to transform multiple design objectives into a single objective function suitable for optimization. Afterwards, the objective function for variability is minimized. Finally, the mean circuit performance measures are fine tuned for given target specifications.

Analysis of two-dimensional effects on subthreshold current in submicron MOS transistors

Abstract In short channel devices, the dependence of subthreshold current on drain induced barrier lowering, substrate bias, channel length, and temperature is modeled. NMOS devices down to effective channel length of 0.13 μm are considered. The model, based on drift-diffusion theory, accurately predicts such dependence as verified by results obtained using this model when compared with those obtained with numerical device simulators.

A new statistical methodology predicting chip failure probability considering electromigration

Abstract We present a new approach to analyze chip reliability due to electromigration (EM). This new approach utilizes the statistical nature of EM failure in order to assess overall EM risk. It includes within-die temperature variations from the chip’s temperature map extracted by an Electronic Design Automation (EDA) tool to estimate the failure probability of a design. We first used the traditional EM approach to analyze the design with a single temperature across the entire chip that involves six metal and five via layers. Next, we used the same traditional approach but with a realistic temperature map. A comparison between these two results confirms that using a temperature map yields a less pessimistic estimation of the chip’s EM risk. Finally, we employed the statistical methodology developed by us considering a temperature map and different use-condition voltages and frequencies to estimate the overall failure probability of the chip. The results of this statistical analysis confirm that the chip level failure probability is higher (i) at higher use-condition frequencies for all use-condition voltages, and (ii) when a single temperature instead of a temperature map across the chip is considered.

Statistical circuit performance variability minimization under manufacturing variations

In this paper, we present a flow to minimize the variability of a circuit performance measure due to the statistical variations in the manufacturing process. The flow starts with 0.18mum worst case corner device model parameters and transforms them to uncorrelated random variables for the statistical design of experiments which generate response surface models (RSM) of the circuit variability in terms of the circuit designable parameters. The minimization of variance due to process fluctuations is performed on the RSM functions by changing the circuit designable parameters, such as channel widths of the devices without causing excessive mean response shifts. Finally, the mean response is re-adjusted using the designable parameters that are not used in the variability minimization

A new statistical electromigration analysis methodology that incorporates across-chip temperature variation

In this paper, we present a new approach which uses statistical methods to analyze the Electromigration (EM) reliability on a chip. This new approach utilizes statistical nature of EM failure distribution to assess overall EM risk of a product. Furthermore, we have incorporated within-die temperature variation into the proposed EM analysis to better estimate the EM risk of a product.

Fringe field and quantum mechanical effects on capacitance characteristics of sub-0.1 micron MOS devices

In this paper, we compare the 3D VQM expressions obtained for the capacitive energy of the oxide region and the depletion region with those for a device with infinitely large gate. The 3D quantum mechanical effect of the fringe field on the energy is then extracted as a correction factor to the capacitance for each region.

A novel variational approach for modeling sub-0.1 micron MOS devices including Quantum Mechanical interface charge confinement effects

In this work we develop and demonstrate a novel variational methodology for modeling deep sub-micron (10 nm-100 nm) three-dimensional (3D) MOS devices that includes the important Quantum Mechanical (QM) interface charge confinement effect.

Statistical Electromigration analysis of a chip with the consideration of a within-die temperature map

In this paper, we present a new approach which uses statistical methods to analyze the Electromigration (EM) reliability of a chip. This new approach utilizes statistical nature of EM failure distribution to assess overall EM risk and applies a within-die temperature map on a chip level design of multiple metal and via layers. The new proposed method provides a more optimistic EM violation estimation result when compared with results using traditional method.

A simple variational technique for estimating quantum mechanical charge redistribution effects in deep sub-micron MOS devices

We have developed and demonstrated the application of variational methods in calculation of the effect of quantum mechanical (QM) charge confinement at the metal oxide semiconductor (MOS) Si-SiO/sub 2/ interface, and its perturbation on the threshold voltage, V/sub th/ as a function of doping concentration.

Single-electron-transistor behavior in deep sub-0.1 /spl mu/m planar-doped-barrier FETs

Planar-doped-barrier FETs (PDBFETs) show low-temperature current measurements similar to those of single-electron-transistors (SETs). Also, it appears from simulation that a dynamic LDD-like region in the PDBFET is created when the device is under gate bias. This paper discusses the concept of an N-PDBFET working as a SET. Under no gate bias, the silicon band-gap forms a large barrier which prevents tunneling from occurring. In addition, the region underneath the valence band can be treated as a quasi-continuum. However, under gate bias, the barrier produced by the silicon band-gap is narrowed significantly and discrete energy levels begin to appear under the valence energy band, enabling electrons to tunnel through the available valence energy states. Similarly, in P-PDBFETs, hole tunneling through available conductance energy states occurs.