Mohamed A. Sheirah

FPGA based accelerator for functional simulation

We introduce an FPGA-based approach to accelerate functional simulation. We achieve speedups between 5 and 100X over pure software simulation. This approach takes advantage of a simulators software procedural interface, provided by a commercial VHDL simulator. Our approach uses the master-slave co-simulation technique. The master is the HDL simulator, which controls the time advance mechanism. The slave is an FPGA board, where the DUT is synthesized in hardware. In the middle, we developed a communication library responsible for communicating the flow of events and values between both sides.

Code synthesis for timed automata: a comparison using case study

There are two available approaches to automatically generate implementation code from timed automata model. The first approacch is implemented and attached to TIMES tool [1]. We will call this approach “TIMES approach”. While the second approach is based on using B-method [2] and its available code generation tool [3]. We will call this approach “B-method approach”. We select the model of the production cell to be used as a case study for the comparison between these two approaches. The same production cell model has been used against both approaches. The B-method approach generates platform independent code [4]. So we select the generated code using TIMES to be platform independent too for the comparison purpose. For the B-method approach, we use the deterministic semantic of timed automata which is used for TIMES code generation as given in [5]. This semantic controls the selection of the next executed function. The using of this deterministic mechanism is generally not needed for the code generated by the B-method approach. But we use it as it is the implemented mechanism for the TIMES approach. So we select to use it for comparison purpose. By running the implementation code generated using the B-method approach, it works fine as far as we run and no property violation could be found. On the other hand the code generated using TIMES approach runs successfully for the first 10 action transitions and then it progresses the time infinitely. This means that the system deadlocked, so it violates the first property of the model. While the first property is to guarantee that the system is deadlock free. This deadlock is due to the mishandling of the committed and urgent states [6]. The introduced comparison gave a result that the approach based on the using of B-method generates a verified code (by mean of simulation) and handles more timed automata features.

Accelerated cosimulation using reconfigurable computing

Reconfigurable computing is becoming an important part of research in computer architecture and software systems. The principal benefits of reconfigurable computing are their ability to realize the flexibility of a software-based solution while retaining the execution speed of a more traditional, hardware-based approach. A great acceleration in the simulation time of digital circuits can be achieved by making a configurable device behave exactly as a given circuit. Simulation is then conducted on this hardware device instead of a software simulator.

Mapping timed automata to B

This paper presents the approach of the translation from timed automata into B-method. We are modeling using a network of timed automata, extended with data types, which is the modeling language used for UPPAAL tool and convert this model into B-method system. The integration of UPPAAL and B-method gives the advantages of both tools; the UPPAAL modeling facility and the B-method usability and available tools.

Identification and control of nonlinear processes using neural network

In this paper, a dynamic model of the magnet levitation nonlinear process is identified as a neural network. The accuracy of the model is tested and verified even if the observed input/output data contains noisy components. Three layers neural network controller is proposed and developed in order to track the set point and regulate against disturbance. The response of the proposed neural controller is tested and verified. Simulation results show the power of neural network to model and control nonlinear processes.

A security layer for smart card applications authentication

This paper briefly describes what is a smart card and its standard authentication schemes. Additionally, this paper provides high level overview of code signing mechanisms, which serve the purpose to ensure the smart card application (possible provided by 3rd Party Application Provider) is genuine and from an authorized provider.

Reliable Target Prediction Using Interception Triangle

In this paper, a new reliable algorithm is proposed to predict the missile-target interception point. It uses the interception-triangle to exactly determine the interception point. It considers actual measurement values for both missile and target position. Also, it considers measurement errors, additive noise, jamming and transmission delay. The whole technique is implemented over a realistic nonlinear missile model. This model include most of missile dynamics, nonlinearities, different coordinate systems, actuator devices, measuring and tracking devices like earth fixed radar, on board target tracker, global positioning system and more. Simulation results and comparison with existing technique for different missile-target engagement are illustrated to validate the propose technique.