B. Benbakhti

193nm deep-ultraviolet solar-blind cubic boron nitride based photodetectors

Deep-ultraviolet (DUV) solar-blind photodetectors based on high-quality cubic boron nitride (cBN) films with a metal/semiconductor/metal configuration were fabricated. The design of interdigitated circular electrodes enables high homogeneity of electric field between pads. The DUV photodetectors present a peak responsivity at 180nm with a very sharp cutoff wavelength at 193nm and a visible rejection ratio (180 versus 250nm) of more than four orders of magnitude. The characteristics of the photodetectors present extremely low dark current, high breakdown voltage, and high responsivity, suggesting that cBN films are very promising for DUV sensing.

Effects of Self-Heating on Performance Degradation in AlGaN/GaN-Based Devices

A self-consistent electrothermal transport model that couples electrical and thermal transport equations is established and applied to AlGaN/GaN device structures grown on the following three different substrate materials: 1) SiC; 2) Si; and 3) sapphire. Both the resultant I-V characteristics and surface temperatures are compared to experimental I -V measurements and Raman spectroscopy temperature measurements. The very consistent agreement between measurements and simulations confirms the validity of the model and its numerical rendition. The results explain why the current saturation in measured I-V characteristics occurs at a much lower electric field than that for the saturation of electron drift velocity. The marked difference in saturated current levels for AlGaN/GaN structures on SiC, Si, and sapphire substrates is directly related to the different self-heating levels that resulted from the different biasing conditions and the distinctive substrate materials.

Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures

Abstract The effect of interface state trap density, D it , on the current–voltage characteristics of four recently proposed III–V MOSFET architectures: a surface channel device, a flat-band implant-free HEMT-like device with δ -doping below the channel, a buried channel design with δ -doping, and implant-free quantum-well HEMT-like structure with no δ -doping, has been investigated using TCAD simulation tools. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current. The distributions of interface states having high density tails that extend to the conduction band can significantly impact the subthreshold performance in both the surface channel design and the implant-free quantum-well HEMT-like structure with no δ -doping. Furthermore, the same distributions have little or no impact on the performance of both flat-band implant-free and buried channel architectures which operate around the midgap.

Analysis of Thermal Effect Influence in Gallium-Nitride-Based TLM Structures by Means of a Transport–Thermal Modeling

The power dissipation in a semiconductor device usually generates a self-heating effect, which becomes very significant for gallium nitride power applications. The operating temperature of these devices increases significantly, and the transport properties are then degraded (IEEE Electron Device Lett., vol. 24, p. 375, 2003; IEEE Electron Device Lett., vol. 49, p. 1496, 2002; IEEE Trans. Electron Devices, vol. 52, p. 1683, 2005). Taking heating effects into account explains the physical phenomena observed in experiments, due in particular to the fact that temperature greatly affects the velocity. In this paper, numerical simulations are carried out to study the influence of thermal effects on the static characteristics of GaN transmission line measurement (TLM) model structures. A transport-thermal model is thus developed in order to take into account both the electrical and the thermal phenomena in a coupled way. This paper uses GaN TLMs on sapphire substrates. Simulations have shown that the saturation current is reached for electric fields much lower than the saturation electric field, thus confirming the experimental results

Characterization of Electron Traps in Si-Capped Ge MOSFETs With

Si-capped Ge MOSFETs have good compatibility with existing processes, and promising results have been reported. The process is becoming sufficiently mature to warrant assessment of device reliability. Good time-dependent dielectric breakdown performance has been observed, and negative-bias-temperature-instability susceptibility is better than Si counterparts. Electron trapping is shown to be problematic and affects devices through positive bias temperature instability and hot carrier injection. This letter characterizes electron trapping in HfO₂/SiO₂ stacks on Si-capped Ge. Trapping is substantial, increasing with <i>VG</i> and reaching ~ 10¹³ cm^-2 in 100 μs under <i>VG</i> = 2.0 V. We report, for the first time, two distinctive capture cross sections (CCS) by measuring the transient gate current. The large CCS can be ~ 10^-12 cm² and reduces for a higher oxide field, which is a signature of coulombic attractive centers. The small CCS is on the order of 10^-14 cm², which is a typical value found for electron traps in SiO₂ and HfO₂/SiO₂ stacks on Si.

\hbox{HfO}_{2}/\hbox{SiO}_{2}

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3-GeO2-Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3/GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3/GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise.

Gate Stack

A detailed analysis of nonequilibrium electron transport in n-type Si and In0.3Ga0.7As MOSFETs scaled into ultimate limit of 5-nm gate length is carried out using ensemble Monte Carlo device simulations. The analysis is based on simulations of ID-VG characteristics for a template, 25-nm gate length Si MOSFET compared against previous results from various Monte Carlo device codes, and for an equivalent 25-nm gate length In0.3Ga0.7As MOSFET. The transistors are then laterally scaled from a gate length of 25 nm to 20, 15, 10 and 5 nm monitoring the average electron velocity, energy, and sheet density along the channel at a supply voltage of 1.0 V. A degradation of the injection velocity with the scaling of a gate/channel length is observed. While we have found a decrease in the overall electron velocity profile along the Si channel for gate lengths smaller than 10 nm and a decrease in the injection velocity from a gate length of 20 nm, the increase in the intrinsic drain current in the scaling process is continuous thanks to the increasing velocity at the drain side. However, the velocity in the InGaAs channel MOSFETs increases steadily during the scaling but the increase in the intrinsic drain current is less pronounced. This is the result of a source starvation, due to a low density of states in III-V semiconductors, which cannot provide a large enough electron sheet density in the channel. This effect is partially mitigated by the enhancement of density of states as a proportion of electrons in the source/drain transfers to upper valleys with a larger electron effective mass.

Energy Distribution of Positive Charges in

Deep-ultraviolet solar-blind photodiodes based on high-quality AlN films grown on sapphire substrates with a metal–semiconductor–metal configuration were simulated and fabricated. The Schottky contact is based on TiN metallization. The material is characterized by the micro-Raman spectroscopy and x-ray diffraction technique. The detector presents an extremely low dark current of 100 fA at −100 V dc bias for large device area as high as 3.1 mm2. It also exhibits a rejection ratio between 180 and 300 nm of three orders of magnitude with a very sharp cut-off wavelength at 203 nm (~6.1 eV). The simulation to optimize the photodiode topology is based on a 2D energy-balance model using the COMSOL® software. Simulation performed for different spacing for a given bias between electrodes show that a compromise must be found between the dark current and the responsivity for the optimization of the device performance. The measurement results are in good agreement with the model predictions.

{\rm Al}_{2}{\rm O}_{3}{\rm GeO}_{2}/{\rm Ge}

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional Vg-accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 °C; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSFETs: their energy levels have a spread below the edge of valence band, i.e., Ev, when neutral, lift well above Ev after charging, and return below Ev following neutralization.

pMOSFETs

An nMOSFET for the future high mobility dual-channel CMOS based on anew In0.53Ga0.47As implant free quantum well architecture is optimized to achieve low leakage and high on-current. Various aspects of its performance are evaluated using the ensemble Monte Carlo technique, calibrated drift-diffusion simulations, and non-equilibrium Greens functions technique. The numerical investigations demonstrate that the implant-free quantum-well nMOSFET has a better electrostatic integrity (a subthreshold slope of ~80 mV/dec and a drain induced barrier lowering of ~40 mV/V) and less sensitivity to the interface states density than the implanted III-V surface channel architectures. We predict a very large drive current with a swift onset for the device with δ-doping on the backside of the channel. For the device variant without δ-doping, we observe the on-current reduction by about 30% and a large influence of thickness of lateral spacers (access regions) on the drive current due to the lack of carriers. Finally, the decrease in the channel thickness results in the increase of a higher valleys contribution into the total current from 4% to 25% when the channel is shrunk from to 2 nm.