B. Flechet

High frequency characterization and modeling of high density TSV in 3D integrated circuits

High frequency characterization and modeling of Through Silicon Vias (TSVs) for new 3D chip staking are presented in this paper. Works focus on high density TSVs, up to 106 cm−2, with pitch below 10 µm and aggressive wafer thinning to maintain TSV aspect ratio in a range between 5 and 10. Equivalent electrical RLCG models of TSVs with height of 15 µm and diameter of 3 µm are extracted up to 20 GHz. It is shown that values extracted for components are directly related to design and material characteristics used to process 3D TSVs.

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits

Through Silicon Via (TSV) is considered today as the third dimension interconnect opening new perspectives in term of 3D integration. Design, material and process recommendations are required to achieve 3D stacked dies and evaluate electrical performance of such chips. As a consequence, equivalent models of this incontrovertible key component become more and more mandatory. In this paper, a full parametric and frequency dependent model of high aspect ratio TSV is proposed based on both electromagnetic (EM) simulations and RF measurements. This model enables to extract TSV resistance, self inductance, oxide capacitance and parasitic elements due to the finite substrate resistivity. Its full compatibility with SPICE solvers allows the investigation of TSV impact on circuit performance.

Investigation on TSV impact on 65nm CMOS devices and circuits

4µm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7µA/µm on the static NMOS drain current. However, the ring oscillators response is not impacted.

Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate modeling of TSV is consequently essential to perform design, material and process optimizations. This paper presents a frequency dependent analytical model including MOS effect of high aspect ratio TSV achieved in a full CMOS 65 nm platform according to a face-to-face Via Last process. Specific test structures with bulk contacts to polarize silicon were integrated enabling C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed and simplified according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) leading to a full analytical model.

Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.

Ferroelectric properties of Pb(Zr,Ti)O3 thin films until 40 GHz

The radio frequency characterization of Cu/TiN/Pb(Zr,Ti)O3 stack on glass is performed using coplanar transmission lines. A dielectric relaxation is evidenced around 10 GHz by the correlated decrease in the dielectric constant K together with the dielectric losses increase versus frequency. This phenomenon is attributed to domain wall relaxation. The ferroelectric nature of Pb(Zr,Ti)O3 (PZT) thin films is observed until 40 GHz with a hysteresis curve of K versus dc bias. The high K value (K∼1200) combined with a high tunability (∼35%) and moderate losses (∼1%) suggest that PZT films could be well suited for tunable devices for frequencies lower than 5 GHz.

Keep on shrinking interconnect size: Is it still the best solution?

According to the evolution between each new technological generation of CMOS ICs, ITRS suggests a reduction in interconnect sizes by a factor of around square root of 2. In this paper a reference design rule is based on a perfectly controlled technology of the CMOS 45 nm node, with interconnects width equal to their separation space. Our works are focused on the impact on signal transmission speed and delay along interconnects of decreasing the space or width. To avoid new industrial manufacturing constraints on cost and reliability, this study is performed without modifying process and materials used in the BEOL of CMOS 45 nm IC. We will study interconnects of 50 nm width, with a 50 nm space between lines in accordance with CMOS 32 nm FEOL requirements. In the second time we will relax geometrical constraints to enlarge the scope of application.

Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking

In 3D integrated circuits, substrate coupling effects due to propagation of High Frequency (HF) parasitic signals are carried by Through Silicon Vias (TSV). These electrical coupling leads to several impacts on performance of 3D circuits. In this paper, predictive HF electrical simulations are achieved by full wave analysis in order to make obvious the coupling effect due to TSVs presence. Solutions to reduce substrate coupling are proposed and discussed.

Integration and frequency dependent parametric modeling of Through Silicon Via involved in high density 3D chip stacking

Evaluation of Through Silicon Via (TSV) electrical performance is hardly required today to improve heterogeneous 3D chip performance in the frame of a “more than Moore” approach. Accurate modeling of TSV is consequently essential to perform design optimizations and process tuning. This paper proposes a methodology based on RF characterizations and simulations, leading to a frequency dependent analytical model including MOS effect of high aspect ratio TSV. Specific test structures integrated on both floating Si bulk and CMOS 65 nm active wafers according to a face-to-face Via Last After Bonding process enable C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) and implemented in SPICE simulator to predict TSV impact on signal propagation.

Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack

TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at low frequencies and radiofrequencies are reported. Simulations are done using a software performing device and electromagnetic co-simulations. The model and simulations are validated by measurements. Simulations to study the sensitivity of the TSV structure to the layout show changes in the TSV-to-substrate coupling behavior.