T. Lacrevaz

Investigation on TSV impact on 65nm CMOS devices and circuits

4µm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7µA/µm on the static NMOS drain current. However, the ring oscillators response is not impacted.

Ferroelectric properties of Pb(Zr,Ti)O3 thin films until 40 GHz

The radio frequency characterization of Cu/TiN/Pb(Zr,Ti)O3 stack on glass is performed using coplanar transmission lines. A dielectric relaxation is evidenced around 10 GHz by the correlated decrease in the dielectric constant K together with the dielectric losses increase versus frequency. This phenomenon is attributed to domain wall relaxation. The ferroelectric nature of Pb(Zr,Ti)O3 (PZT) thin films is observed until 40 GHz with a hysteresis curve of K versus dc bias. The high K value (K∼1200) combined with a high tunability (∼35%) and moderate losses (∼1%) suggest that PZT films could be well suited for tunable devices for frequencies lower than 5 GHz.

Presentation of a new time domain simulation tool and application to the analysis of advanced interconnect performance dependence on design and process parameters

The speed of integrated circuits is increasingly fixed by interconnect performances. To address this issue, the development of new back-end of line technology schemes and materials should be driven by predictions of associated benefits. A new tool was developed and coupled to electromagnetic software to carry out time domain simulations. As a result, the dependences of interconnect performances on process parameters and design rules were extracted for the 65 nm and 45 nm technology nodes.

Optimization of signal propagation performances in interconnects of the 45 nm node by exhaustive analysis of the technological parameters impact

Due to the continuous shrink of technology dimensions, parasitic propagation delay time and crosstalk at interconnect levels increasingly affect overall circuit performances. New materials, processes and architectures are now required to improve BEOL performances. A rigorous high-frequency electromagnetic approach including the scattering effects on Cu line resistance was developed for coupled narrow interconnects to analyze the actual benefits of these innovations for different signal types covering application range from logic to I/O. Effects of advanced metallization (ALD thin barriers), low-k insulators (porous ULKs, low-k barriers), and innovative architectures (hybrid stacks, air gaps, self-aligned barriers) on signal propagation performance were quantified, resulting in an effective process selection for the 45 nm technological node and below.

Impact of ULK restoration techniques on propagation performance for interconnects of the 45 nm technology node and below

The development of advanced ICs architectures for the 45 nm technology node and beyond faces several integration and performance issues. Porous dielectrics are very prone to degradation during process flow, potentially compromising signal integrity. Specific processes such as annealing, restoration treatments, and pore-sealing by liner deposition are considered as potential solutions. Their utility and impact on propagation performance is investigated through both RF measurements and electromagnetic simulations.

Optimization of RF performance of MIM Damascene Capacitors in Backend of Line

High frequency characterizations and simulations of advanced metal-insulator-metal (MIM) capacitors in Cu/low-k backend interconnection process are presented. First, we focus on the impact of silicon substrate and design of MIM capacitors on high frequency performance. Numerical results obtained by a 3D electromagnetic modeling are validated by comparison to experimental results. Second, we show the possibility to increase HF electrical performance of MIM capacitor with optimized design and integration of new medium or high-k materials.