B. H. Hong

Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field-effect transistors

We have investigated the electrical characteristics of cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field effect-transistors with 4nm radius and the gate length ranging from 22to408nm. We observed strong transconductance overshoot in the linear source-drain bias regime in the devices with channel length shorter than 46nm. The mean free path estimated from the slope of the zero-field one dimensional ballistic resistance measured as a function of device length was almost the same as this length.

Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge

We measured and analyzed the subthreshold degradation of the gate-all-around (GAA) silicon nanowire field-effect transistors with the length of 300/500 nm and the radius of 5 nm. An analytical model incorporating the effect of interface traps quantitatively explained the measured subthreshold swing (SS) degradation. A simple electrostatic argument showed that the GAA device had smaller degradation of SS values than planar devices for the same interface trap densities.

Temperature Dependent Study of Random Telegraph Noise in Gate-All-Around PMOS Silicon Nanowire Field-Effect Transistors

We report the random telegraph noise observed in gate-all-around (GAA) PMOS silicon nanowire FETs (SNWFETs) with the radius of 5 nm, at various temperatures (s) down to 4.2 K. From the -dependence of the capture/emission time, we obtain the energy and the charging status of the trap states. The gate bias dependence and the -dependence of the scattering coefficient-mobility product extracted from the relative fluctuation amplitude of the drain current are consistent with the fact that the surface roughness scattering is dominant in GAA PMOS SNWFETs.

Observation of three-dimensional shell filling in cylindrical silicon nanowire single electron transistors

The authors have measured addition energy spectra from gate-all-around twin silicon nanowire single electron transistors (SETs) with the radius of 5nm and with circular cross sections. Nonmonotonically varying addition energies are observed and the authors interpret them as shell fillings of silicon nanowire quantum dots with three-dimensional harmonic confinement potentials. A 45nm long SET shows 2-1-2-1 filling behavior while a 38nm long SET exhibits 1-2-2-1 filling. These filling behaviors match with the calculated degeneracies of nanowires with different confinement strengths.

Quantitative Extraction of Temperature-Dependent Barrier Height and Channel Resistance of a-SIZO/OMO and a-SIZO/IZO Thin-Film Transistors

Temperature (T)-dependent electrical characteristics of thin-film transistors fabricated using oxide-metal-oxide (OMO) and indium-zinc-oxide (IZO) as electrodes and amorphous silicon-doped IZO (a-SIZO) as channel material were studied. The measured data were fit, using a Schottky diode/resistor/Schottky-diode-equivalent circuit model, to obtain the barrier height and the channel resistance. The barrier height coefficients α of the IZO and OMO electrode devices were found to be 1.59 and 1.61 meV/K, respectively. The T-dependent resistivity of the a-SIZO channel material was consistent with the variable range hopping conduction mechanism.

Correction to “Quantitative Extraction of Temperature-Dependent Barrier Height and Channel Resistance of a-SIZO/OMO and a-SIZO/IZO Thin-Film Transistors” [Feb 13 247-249]

In the above paper (ibid., vol. 34, no. 2, pp. 247-249, Feb. 2013), the information for corresponding authors is not correctly indicated. Authors S. Kim, S. Y. Lee, and S. W. Hwang are the corresponding authors for this paper. Their information can be found at the bottom of this page.

Capacitive coupling model and extraction of the molecular interface states in porphyrin-silicon nanowire hybrid field-effect transistor

We modeled and extracted the distribution of interface trap density by grafted molecules on the surface of a silicon nanowire field-effect transistor (SNWFET). The subthreshold current model was employed, and the capacitive coupling model of ideality factor was simplified, using a fully depleted SNWFET. We applied the analytical model to p-channel SNWFET with porphyrin, and extracted the distribution of the molecular interface states. There were 748 and 474 traps (average value) in length (L) = 300 nm and L = 500 nm devices, respectively. The trap energy was in the range of 0.27–0.35 eV.

Co-existence of Random Telegraph Noise and Single-Hole-Tunneling State in Gate-All-Around PMOS Silicon Nanowire Field-Effect-Transistors

Low temperature hole transport characteristics of gate-all-around p-channel metal oxide semiconductor (PMOS) type silicon nanowire fieldeffect-transistors with the radius of 5 ㎚ and lengths of 44-46 ㎚ are presented. They show coexisting two single hole states randomly switching between each other. Analysis of Coulomb diamonds of these two switching states reveals a variety of electrostatic effects which is originated by the potential of a single hole captured in the trap near the nanowire.

Transport through single dopants in gate-all-around silicon nanowire MOSFETs (SNWFETs)

Temperature (T) dependent transport measurements of cylindrical shaped gate-all-around silicon nanowire MOSFETs (SNWFETs) were performed. Single electron tunneling behaviors were observed at 4.2 K and one of the devices exhibited anomalously strong current peak which survived even at room temperature. The observed peak was interpreted as an evidence of transport through single impurities in the channel.

Temperature dependent transport characteristics of multi-bridge-channel MOSFETs (MBCFETs)

Recently, having vertically stacked arrays of 3D channels, multi-bridge-channel MOSFETs (MBCFETs) have been fabricated successfully (Lee et al., 2003). In this paper, we report temperature dependent transport characteristics of the MBCFET.