Dong-sik Park

Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field-effect transistors

We have investigated the electrical characteristics of cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field effect-transistors with 4nm radius and the gate length ranging from 22to408nm. We observed strong transconductance overshoot in the linear source-drain bias regime in the devices with channel length shorter than 46nm. The mean free path estimated from the slope of the zero-field one dimensional ballistic resistance measured as a function of device length was almost the same as this length.

Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge

We measured and analyzed the subthreshold degradation of the gate-all-around (GAA) silicon nanowire field-effect transistors with the length of 300/500 nm and the radius of 5 nm. An analytical model incorporating the effect of interface traps quantitatively explained the measured subthreshold swing (SS) degradation. A simple electrostatic argument showed that the GAA device had smaller degradation of SS values than planar devices for the same interface trap densities.

Temperature Dependent Study of Random Telegraph Noise in Gate-All-Around PMOS Silicon Nanowire Field-Effect Transistors

We report the random telegraph noise observed in gate-all-around (GAA) PMOS silicon nanowire FETs (SNWFETs) with the radius of 5 nm, at various temperatures (s) down to 4.2 K. From the -dependence of the capture/emission time, we obtain the energy and the charging status of the trap states. The gate bias dependence and the -dependence of the scattering coefficient-mobility product extracted from the relative fluctuation amplitude of the drain current are consistent with the fact that the surface roughness scattering is dominant in GAA PMOS SNWFETs.

Observation of three-dimensional shell filling in cylindrical silicon nanowire single electron transistors

The authors have measured addition energy spectra from gate-all-around twin silicon nanowire single electron transistors (SETs) with the radius of 5nm and with circular cross sections. Nonmonotonically varying addition energies are observed and the authors interpret them as shell fillings of silicon nanowire quantum dots with three-dimensional harmonic confinement potentials. A 45nm long SET shows 2-1-2-1 filling behavior while a 38nm long SET exhibits 1-2-2-1 filling. These filling behaviors match with the calculated degeneracies of nanowires with different confinement strengths.

Novel Approach for the Reduction of Leakage Current Characteristics of 20 nm DRAM Capacitors With ZrO 2 –Based High-k Dielectrics

In order to produce a dynamic random access memory (DRAM) of 20 nm or less, the most important concern regarding development is to reduce the leakage current degradation of the capacitor using high-k dielectrics. We studied the effect of defect sources present after the formation of the capacitor and measured the leakage current characteristics of the capacitor using the dielectric breakdown degradation test, a test used in mass production. From these results, we confirmed that the leakage current degradation was completely eliminated by removing external impurities of boron and hydrogen without any change in the structure or materials of the capacitor. For further DRAM scaling, we propose a method of reducing leakage current degradation of the capacitor.

Transport through single dopants in gate-all-around silicon nanowire MOSFETs (SNWFETs)

Temperature (T) dependent transport measurements of cylindrical shaped gate-all-around silicon nanowire MOSFETs (SNWFETs) were performed. Single electron tunneling behaviors were observed at 4.2 K and one of the devices exhibited anomalously strong current peak which survived even at room temperature. The observed peak was interpreted as an evidence of transport through single impurities in the channel.