Sung-dae Suk

Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field-effect transistors

We have investigated the electrical characteristics of cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field effect-transistors with 4nm radius and the gate length ranging from 22to408nm. We observed strong transconductance overshoot in the linear source-drain bias regime in the devices with channel length shorter than 46nm. The mean free path estimated from the slope of the zero-field one dimensional ballistic resistance measured as a function of device length was almost the same as this length.

Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application

We have successfully fabricated sub 30nm N+ poly and TiN gate MBCFET (multi-bridge-channel field effect transistor) both on SOI wafers and bulk-Si wafers. Using TiN metal gate and 20nm multi bridge channels, we achieved the drive current of 2.3mA//spl mu/m that is the largest drive current ever reported for pMOSFETs with excellent subthreshold swing of 75mV/dec, and drain induce barrier lowering (DIBL) of 36mV/V. Large I/sub on//I/sub off/ ratio and excellent threshold voltage (V/sub t/) distribution were obtained using TiN metal gate to eliminate channel ion implantation minimizing the mobility degradation and dopant fluctuation.

Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application

Improving the MBCFET performance further, we have successfully fabricated single-metal-gate high-performance CMOS MBCFET with elevated flat source/drain (EF-S/D) formed by low temperature cyclic selective epitaxial growth (LTC-SEG) of Si. Due to the S/D engineering and LTC-SEG process, we could achieved the symmetric threshold voltage of 0.25V and -0.22V for TiN-gate n-channel MBCFET (nMBCFET) and p-channel MBCFET (pMBCFET), respectively. This single-metal MBCFET simultaneously satisfied the requirements of high-performance (HP) and low operating power (LOP) transistors in ITRS roadmap.

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

Observation of three-dimensional shell filling in cylindrical silicon nanowire single electron transistors

The authors have measured addition energy spectra from gate-all-around twin silicon nanowire single electron transistors (SETs) with the radius of 5nm and with circular cross sections. Nonmonotonically varying addition energies are observed and the authors interpret them as shell fillings of silicon nanowire quantum dots with three-dimensional harmonic confinement potentials. A 45nm long SET shows 2-1-2-1 filling behavior while a 38nm long SET exhibits 1-2-2-1 filling. These filling behaviors match with the calculated degeneracies of nanowires with different confinement strengths.

Possibility of Transport Through a Single Acceptor in a Gate-All-Around Silicon Nanowire PMOSFET

Temperature-dependent electrical transport measurements of cylindrical shaped gate-all-around silicon nanowire p-channel MOSFET were performed. At 4.2 K, they show current oscillations, which can be analyzed by single hole tunneling originated from nanowire quantum dots. In addition to this single hole tunneling, one device exhibited strong current peaks, surviving even at room temperature. The separations between these current peaks corresponded to the energy of 25 and 26 meV. These values were consistent with the sum of the bound-state energy spacing and the charging energy of a single boron atom. The radius calculated from the obtained single-atom charging energy was also comparable to the light-hole Bohr radius.

TiN/HfSiOx Gate Stack Multi-Channel Field Effect Transistor (McFET) for Sub 55nm SRAM Application

For the first time, titanium-nitride (TiN) single metal gate and high-k hafnium-silicate (HfSiO_x) gate dielectric have been successfully integrated in 55nm McFET SRAM cell. The use of HfSiO_x gate dielectric, not only reduces gate leakage current but also improves I_ON/I_OFF ratio of PFET to 10⁸. Using local fin implantation (LFI) scheme, junction capacitance is reduced by 13% and junction breakdown voltage is increased by 1.4V

Transport through single dopants in gate-all-around silicon nanowire MOSFETs (SNWFETs)

Temperature (T) dependent transport measurements of cylindrical shaped gate-all-around silicon nanowire MOSFETs (SNWFETs) were performed. Single electron tunneling behaviors were observed at 4.2 K and one of the devices exhibited anomalously strong current peak which survived even at room temperature. The observed peak was interpreted as an evidence of transport through single impurities in the channel.

Single-metal gate multi-bridge-channel MOSFET (MBCFET) for CMOS application

Simplifying the MBCFET process further, the authors have successfully fabricated single-metal-gate CMOS MBCFET. Due to channel engineering, the symmetric threshold voltage of 0.25V and -0.22V for single TiN-gate n-channel MBCFET (nMBCFET) and p-channel MBCFET (pMBCFET), could be achieved respectively.