B.J.S. De Loore

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.

IC for motion-compensated 100 Hz TV with smooth-motion movie-mode

An IC for consumer 100 Hz television is presented. It applies motion estimation and compensation techniques for very high-quality field rate up-conversion and a judder-free motion portrayal of movie material. The IC is fabricated with an 0.8 /spl mu/m CMOS process.

A video signal processor for motion-compensated field-rate upconversion in consumer television

In todays 100 Hz television sets, the display rate is doubled by displaying incoming fields twice. Moving objects are displayed at an incorrect position in the interpolated fields. In the new generation 100 Hz television sets, this artifact is solved by motion-compensated interpolation. Known algorithms for motion estimation and compensation require a huge number of computations. A 3D-recursive block matching algorithm makes possible a one-chip solution. The presented IC is also capable of jitter-free motion portrayal of movie material (25 Hz to 60 Hz upconversion), noise reduction, and vertical zoom.

A high-quality digital audio filter set designed by silicon compiler CATHEDRAL-1

The semi-automatic design and custom integration of a high-quality digital audio preamplifier filter set are described. The set consists of an offset filter, ten graphic equalizer sections, and a scratch filter with a worst-case overall signal-to-noise ratio of 10 dB. The silicon compiler CATHEDRAL-1 supports the design from specifications to layout. The combination of efficient synthesis tools with optimisation at all design levels leads to a very compact silicon integration, compared with a general-purpose signal processor approach. An experimental chip is described on which the offset filter, three equalizer sections, and the scratch filter are integrated. The silicon area is 243 mm/SUP 2/ in a conservative 6-/spl mu/m NMOS technology or 8 mm/SUP 2/ when scaling down to 3-/spl mu/m technology, allowing for functional densities up to 0.2 mm/SUP 2/ pole zero, comparable with area requirements for typical switched-capacitor filters. The total filter set requires only 20 mm/SUP 2/ in a 3-/spl mu/m NMOS technology, which demonstrates the potential for low-cost digital high-fidelity signal processing.

Automatic verification of library-based IC designs

A novel method for fully automatic verification of layout generated by means of a library is presented. It is based on the bottom-up reconstruction of the architecture level, starting from layout. The benefits have been confirmed during the verification of VLSI circuits generated with the PIRAMID silicon compiler. Previously unnoticed design and synthesis errors have been detected in a very efficient way.<<ETX>>

The design of a competitive ASIC for the consumer market using the PIRAMID design system

Architecture synthesis tools have been used to design a commercial ASIC for the consumer market. The IC was subject to stringent time-to-market and efficiency constraints. The PIRAMID design system was used to meet both constraints. The integration of state-of-the-art architecture synthesis, test pattern generation, layout generation, and design verification techniques is shown to be of crucial importance to increase design speed. The design of a top-of-the-line multifunctional bit-stream stereo digital audio filter using the PIRAMID silicon compiler is described.<<ETX>>

Application specific integrated filters for HIFI digital audio signal processing

The semi-automatic design and integration of a digital audio preamplifier filter set is discussed. The set consists of an offset filter, 10 graphic equalizer sections and a scratch filter with an overall signal-to-noise ratio of 100 dB. A silicon compiler CATHEDRAL-I supports the design cycle from specifications to layout; the combination of synthesis with optimization tools at all design levels leads to a very compact silicon integration. An experimental chip integrates the offset filter, 3 equalizer sections and the scratch filter. The area is 24, 3mm2in coservative 6µm NMOS or 8mm2when scaling down to 3µm technology, allowing for functional densities up to 0.2 mm2/pole-zero. This demonstrates the potential for very cheap digital HIFI signal processing.The semi-automatic design and integration of a digital audio preamplifier filter set is discussed. The set consists of an offset filter, 10 graphic equalizer sections and a scratch filter with an overall signal-to-noise ratio of 100 dB. A silicon compiler CATHEDRAL-I supports the design cycle from specifications to layout; the combination of synthesis with optimization tools at all design levels leads to a very compact silicon integration. An experimental chip integrates the offset filter, 3 equalizer sections and the scratch filter. The area is 24, 3mm2in coservative 6µm NMOS or 8mm2when scaling down to 3µm technology, allowing for functional densities up to 0.2 mm2/pole-zero. This demonstrates the potential for very cheap digital HIFI signal processing.