Baofu Zhu

14nm FinFET technology for analog and RF applications

This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET RF performance compared to 28nm technology is due to a source/drain stressor mobility improvement. A benefit of better FinFET channel electrostatics can be seen in the self-gain (Gm/Gds), which shows a significant increase to 40 and 34 for NFET and PFET respectively. Superior 1/f noise of 17/35 f(V∗μm)2/Hz @ 1KHz for N/PFET respectively is also achieved. To extend further low voltage operation and power saving, ultra-low Vt devices are also developed. Furthermore, a deep N-well (triple well) process is introduced to improve the ultra-low signal immunity from substrate noise, while offering useful devices like VNPN and high breakdown voltage deep N-well diodes. A superior Ft/Fmax, high self-gain, low 1/f noise and substrate isolation characteristics truly extend the capability of the 14nm FinFETs for analog and RF applications.

Contact model based on TCAD-experimental interactive algorithm

This work demonstrated a novel method utilizing Sentaurus Technology Computer Aided Design simulation along with experiments to intermediately extract Schottky barrier height and contact resistance in FinFETs. The proposed algorithm can automatically calibrate contact model based on measurement data. This interactive contact model is also capable of prediction of contact resistance sensitivity including key process features such as implant energy, dose and thermal process based on a design of experiment splits. This robust, physical and efficient contact model provides insightful understandings of the metal-semiconductor contact in FinFETs. It can be easily implemented in simulation tools for device design in state-of-art semiconductor technology development.

Influence of stress induced CT local layout effect (LLE) on 14nm FinFET

In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ∼20% current change. NFET performance is enhanced by ∼7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is fully analyzed and explained by the tensile stress induced in the inter-layer dielectric (ILD).