Shesh Mani Pandey

Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond

Fin-based analog, passive, RF and ESD devices have serious performance challenges, such as poor ideality, higher leakage, low breakdown voltage (BV) of diodes, BJTs with poor ideality, mismatch, weak re-surf action and low drain current(Id/μm) of Laterally diffused MOS (LDMOS), degraded RF and 1/f noise of analog CMOS, etc. Innovative solutions which maintain process simplicity and low cost are described in this paper. These new device designs demonstrate excellent performance, such as near perfect-ideality(η)≈1.01 diodes, low leakage, high BV, and BJTs with excellent analog behavior. Fin-based LDMOS and ESD devices outperform conventional planar devices in terms of Id/μm and ESD human body model (HBM) performance, respectively.

14nm FinFET technology for analog and RF applications

This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET RF performance compared to 28nm technology is due to a source/drain stressor mobility improvement. A benefit of better FinFET channel electrostatics can be seen in the self-gain (Gm/Gds), which shows a significant increase to 40 and 34 for NFET and PFET respectively. Superior 1/f noise of 17/35 f(V∗μm)2/Hz @ 1KHz for N/PFET respectively is also achieved. To extend further low voltage operation and power saving, ultra-low Vt devices are also developed. Furthermore, a deep N-well (triple well) process is introduced to improve the ultra-low signal immunity from substrate noise, while offering useful devices like VNPN and high breakdown voltage deep N-well diodes. A superior Ft/Fmax, high self-gain, low 1/f noise and substrate isolation characteristics truly extend the capability of the 14nm FinFETs for analog and RF applications.

Methodology to achieve planar technology-like ESD performance in FINFET process

Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume compared to their counterparts in bulk planar process is compensated with the additional deep implants. The selected ESD devices in Finfet process show competitive ESD performance without any significant cost adder.

Enhanced nFinFET ESD performance

A very simple and useful scheme to enhance the ESD performance of the nFinFET is proposed. By incorporating the N-Well (NW) with the nFinFET, it becomes a low holding-voltage SCR if the NW contact is ohmic and becomes a high holding-voltage SCR if the NW contact is a Schottky contact.

Contact model based on TCAD-experimental interactive algorithm

This work demonstrated a novel method utilizing Sentaurus Technology Computer Aided Design simulation along with experiments to intermediately extract Schottky barrier height and contact resistance in FinFETs. The proposed algorithm can automatically calibrate contact model based on measurement data. This interactive contact model is also capable of prediction of contact resistance sensitivity including key process features such as implant energy, dose and thermal process based on a design of experiment splits. This robust, physical and efficient contact model provides insightful understandings of the metal-semiconductor contact in FinFETs. It can be easily implemented in simulation tools for device design in state-of-art semiconductor technology development.

Advanced TCAD simulation of local mismatch in 14nm CMOS technology FinFETs

Local statistical variability (mismatch) is very important in advanced CMOS technologies critically affecting, among others, SRAM supply and holding voltages, performance and yield. TCAD simulation of statistical variability is essential for identification of variability sources and their control in the technology development and optimization. It also plays an important role in the development of accurate statistical compact models for SRAM design, statistical standard cell characterization and statistical circuit simulation and verification. In this paper we compare the TCAD simulation results of statistical variability in 14nm CMOS FinFET technology with Silicon measurements in order to understand the relative role of key statistical variability sources, to assist the technology optimization and to generate target characteristics for statistical compact model extraction.

Influence of stress induced CT local layout effect (LLE) on 14nm FinFET

In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ∼20% current change. NFET performance is enhanced by ∼7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is fully analyzed and explained by the tensile stress induced in the inter-layer dielectric (ILD).

Modeling the impact of the vertical doping profile on FinFET SRAM V T mismatch

The basic multi-gate Vt variation model for uniform doping is extended to support a 2-region fin doping methodology that provides good agreement with Vt mismatch measurements as well as useful insights into how the non-uniform fin doping impacts the mismatch. The methodology displays good agreement for both NMOS and PMOS SRAM devices from a FinFET process. The NMOS Vt mismatch as a function of Vt is found to follow the non-uniform doping model while the PMOS Vt mismatch is higher due to both high, non-uniform doping as well as P-metal gate workfunction induced mismatch.

Investigation of performance limiting factors of sub-10nm III-V FinFETs

As scaling of transistor continues, there is strong impetus to replace Si with attractive alternate channel materials like InGaAs that would provide high on-current at low voltages. However, many key technology issues need to be addressed and in this paper, we present a rigorous investigation into the performance limiting factors of III-V FinFETs using a 3D Monte-Carlo simulation methodology.

Impact of backplane configuration on the statistical variability in 22nm FDSOI CMOS

In this paper, using variation aware device simulation, we study the local device variability and mismatch as affected by statistical variation resulting from differing backplane doping options in fully depleted SOI transistors. It is seen that discrete random doping effects associated with the choice of doping has a direct effect on mismatch, resulting in increased mismatch with larger channel doping. However, it is also seen that increased backplane doping may counter intuitively help to reduce the variability associated with discrete doping due modification of the electrostatic screening of the source/drain extensions.