Srikanth Samavedam

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

High performance bulk planar 20nm CMOS technology for low power mobile applications

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Continuous process-level and system-level innovation has driven Moores Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET, in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.

Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond

Fin-based analog, passive, RF and ESD devices have serious performance challenges, such as poor ideality, higher leakage, low breakdown voltage (BV) of diodes, BJTs with poor ideality, mismatch, weak re-surf action and low drain current(Id/μm) of Laterally diffused MOS (LDMOS), degraded RF and 1/f noise of analog CMOS, etc. Innovative solutions which maintain process simplicity and low cost are described in this paper. These new device designs demonstrate excellent performance, such as near perfect-ideality(η)≈1.01 diodes, low leakage, high BV, and BJTs with excellent analog behavior. Fin-based LDMOS and ESD devices outperform conventional planar devices in terms of Id/μm and ESD human body model (HBM) performance, respectively.

Anti-fuse memory array embedded in 14nm FinFET CMOS with novel selector-less bit-cell featuring self-rectifying characteristics

A novel anti-fuse memory array is presented in this paper featuring one-capacitor (1C) per bit-cell design and fully compatible with 14nm FinFET CMOS technology. The rectifying I-V characteristics of the metal-insulator-semiconductor (MIS) structure after programming prevents the sneak current in the cross-point array, therefore no need for select transistor in each cell. Thus enables the smallest reported bit-cell with area measuring 0.036 μm2.

14nm FinFET technology for analog and RF applications

This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET RF performance compared to 28nm technology is due to a source/drain stressor mobility improvement. A benefit of better FinFET channel electrostatics can be seen in the self-gain (Gm/Gds), which shows a significant increase to 40 and 34 for NFET and PFET respectively. Superior 1/f noise of 17/35 f(V∗μm)2/Hz @ 1KHz for N/PFET respectively is also achieved. To extend further low voltage operation and power saving, ultra-low Vt devices are also developed. Furthermore, a deep N-well (triple well) process is introduced to improve the ultra-low signal immunity from substrate noise, while offering useful devices like VNPN and high breakdown voltage deep N-well diodes. A superior Ft/Fmax, high self-gain, low 1/f noise and substrate isolation characteristics truly extend the capability of the 14nm FinFETs for analog and RF applications.

A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

Monolithic 3D IC (M3D) shows degradation in performance compared to 2D IC due to the restricted thermal budget during fabrication of sequential device layers. A transistor-level (TR-L) partitioning design is used in M3D to mitigate this degradation. Silicon validated 14nm FinFET data and models are used in a device-to-system evaluation to compare the TR-L partitioned M3Ds (TR-L M3D) performance against the conventional gate-level (G-L) partitioned M3Ds performance as well as standard 2D IC. Extensive cell-level and system-level evaluation, including various device and interconnect process options, shows that the TR-L M3D provides up to 20% improved performance while still maintaining around 30% power saving compared to standard 2D IC. Additionally, the TR-L partitioning design enables M3D with a simplified process flow that leads to 23% lower cost compared to that of G-L partitioning scheme.

Variation improvement for manufacturable FINFET technology

This works examines the sources of electrical variation for FinFET technology based on silicon data from 90nm contacted poly pitch, dual-epitaxy, and RMG (replacement metal gate) transistor. A simple statistical model is used to predict electrical variation based on physical variation that can be measured much earlier in the processing flow. The model is also used to define specification and control limits for physical variation to support the electrical variation specified in SPICE models. Gate stack, Junction, and Gate height variation are identified to be the key contributors to threshold voltage variation for FinFET technology. A case study is also presented on controlling gate height to the desired specification limits by improving across chip, within wafer, wafer to wafer, and lot to lot variation at multiple process steps.

Effective work-function control technique applicable to p-type FinFET high-k/metal gate devices

Abstract In this work, we investigated the effect of so-called WF (Work Function) setting anneal (high temperature annealing on TiN/HfO 2 stack) on gate stack properties. It was found that intermixed layer created in-between TiN and HfO 2 during WF setting anneal has negative fixed charge and reduces pFET V t (positive V t shift). In addition, higher anneal temperature further reduces pFET V t while keeping nFET V t almost unchanged. This could be explained by passivation of oxygen vacancies in HfO 2 with diffused oxygen from TiN layer. By combining these effects, one can further push effective work function towards valence band edge which enables wider coverage of transistor V t option.

Novel N/PFET Vt control by TiN plasma nitridation for aggressive gate scaling

A novel N/PFET threshold voltage (Vt) control scheme was developed for aggressive gate scaling. TiN plasma nitridation reduces absolute Vt by 100mV for both NFETs and PFETs at the same time without photolithography step increase and performance or reliability penalty. TiN plasma nitridation does not need additional work function metal (WFM) to control Vt and hence allows thicker gate contact metal for low gate resistance and improved AC performance.