Baoxia Li

Packaging and assembly of 12-channel parallel optical transceiver module

The fabrication process of a 12-channel parallel optical transceiver module developed in our group is presented in this paper. The module is composed of a VCSEL array, a PIN PD array, a VCSEL driver chip, a TIA/LA chip and supporting PCB and connector. A SiOB and its vertical assembly are emphasized as the highlights of the structure of this module, which is promising to effectively reduce the package cost and improve the optical coupling efficiency.

An electrical design and fabrication of a 12-channel optical transceiver with SiP packaging technology

This paper presents an electrical design of a 6.25Gbps×12-channel parallel optical transceiver with SiP packaging technology. Considering such high speed, a low impedance and low noise power distribution network (PDN) is designed to suppress simultaneous switching noise (SSN) and a novel embedded capacitor filter is used to replace the conventional power supply filter. To minimize the impedance discontinuity of electrical channels, a signal integrity (SI) design flow based on Electromagnetic Analysis Method and Circuit Analysis Method is proposed. Following this design flow, the high speed link performs on a large bandwidth. With the electrical design, the optical transceiver is fabricated and tested.

Complementary metal–oxide–semiconductor compatible 1060 nm photodetector with ultrahigh gain under low bias

Falling on the tail of the absorption spectrum of silicon, 1060 nm Si detectors often suffer from low responsivity unless an exceedingly thick absorption layer is used, a design that requires high operation voltage and high purity epitaxial or substrate material. We report an all-silicon 1060 nm detector with ultrahigh gain to allow for low operation voltage (<4  V) and thin (200 nm) effective absorption layer, using the recently discovered cycling excitation process. With 1% external quantum efficiency, a responsivity of 93 A/W was demonstrated in a p/n junction device compatible with the complementary metal-oxide-semiconductor process.

Low-cost high-efficiency 4 channel pluggable parallel optical transceiver using optoelectronic MCM packaging technologies

A compact 4times2-channel parallel optical MCM transceiver with data rates up to 3.125 Gb/s per channel was studied for very short reach (VSR) interconnection. The transceiver was based on 1times4 VCSEL and PD arrays of 850 nm wavelength, and a 12-fiber-ribbon as the transmission medium. Greatly relaxed alignment tolerance and high coupling efficiency between optoelectronic (OE) device arrays and fiber arrays were achieved. The eye-diagram at 2.5 Gb/s was measured under 231-1 pseudorandom bit stream (PRBS).

A 10-Gbps × 12-Channel Pluggable Parallel Optical Transceiver Based on CXP Interface Specifications

Abstract A novel 10-Gbps × 12-channel pluggable parallel optical transceiver is designed and fabricated. Compared with other optical transceivers, this transceiver emphasizes small size, high-density, low power consumption, and high transmission speed. Most importantly, its optical coupling structure is simplified to promote cost-effective large-scale production. This transceiver is electrically pluggable and consists of transmitter and receiver modules linked by parallel multi-mode fibers. Each module consists of a six-layered high-speed, high-density printed circuit board, the size of which is 30 mm × 18 mm × 1 mm, packaged with optoelectronic devices and corresponding control chips. The printed circuit boards not only provide a high-speed electrical connection between the I/O interfaces and high-speed chips, but they also supply power and ground planes to those chips. End-to-end error-free transmission at 10.3125 Gbps was obtained for a 231 − 1 non-return-to-zero pseudo-random bit sequence.

Parasitic parameter extraction and modeling of via of high speed differential pair

Since high speed digital signal interconnection usually consists of differential transmission lines and pairs of via, signals passing through pairs of via need carefully handling for via can be either capacitive or inductive. The modeling of high speed via is critical to match the impedance of a pair of via and differential transmission line. Parasitic parameters of a pair of via such as capacitances and inductances can be extracted by Q3d, a high performance EM parameter extraction software. Several variables are analyzed: the diameter of via, pad, anti-pad, space between the pair of via and position of ground via around the differential signal via. From the simulation results, parasitic parameters have a significant change with these variables changed. At the same time, TDR (Time domain reflection) and S parameter are also simulated by HFSS to verify the parasitic parameters effects. Parameter extraction and modeling with a pair of via is a helpful way for via optimization, which is commonly used in high speed digital signal interconnection, high frequency transceiver and many application areas.

Fabrication and analysis of 2D embedded passive devices in PCB

This paper presents fabrication and electrical characterization of embedded passives in organic multilayered substrates. We have designed and fabricated a test board and a functional application focusing on embedded passives. A test board with two embedded capacitor layers and one embedded resistor layer was used to evaluate capacitance and resistance performance. The functional application was used to evaluate the performance of integrated passive devices (capacitors, resistors and inductors).

Ultra-wideband noise isolation on power distribution network of high-speed package substrate

This paper presents an effective power noise isolation and suppression method in high-speed package substrates, which is based on planar electromagnetic bandgap (EBG) in local area of power/ground plane and embedded capacitor material between the power and ground planes. Compared with the performance of continuous power and ground planes, the proposed structure provides greater than −40dB isolation in S-parameter simulation at frequency above 1GHz, and shows excellent isolation (−70–−140 dB) from 2GHz up to over 30 GHz frequency range. The structure can be used to minimize the risk of power noise interference between different dies from a shared power supply system in board or out of board.

Design optimization and performance verification of multi-channel high-speed optical transceiver package

This article presents optic-electronic system on package, focus on signal integrity design optimization, and analysis method and performance verification of multi-channel two-way high-speed transceiver. Firstly the whole channel link performance is designed against all variables of interest. These variables are used to evaluate the solution at the system level. Signal integrity analysis and optimization of the high-density differential signal pairs on PCB is conducted to optimize impedance and minimize the effects of discontinuity in the electrical channels such as capacitor, via, connector.

A 9pJ/bit SOP optical transceiver with 80 Gbps two-way bandwidth

The high-speed parallel optical transmitter module based on VCSEL/PD array, high-speed specialized integrated circuit, fiber array micro-optical components presents magnificent application and development potential. The coupling alignment between VCSEL/PD array and waveguide array has been reported using silicon optical bench (SiOB) [1–3]. In this paper, A passive coupling method based on SiOB and the packaging of the VCSEL/PD arrays are introduced; the coupling efficiency is about 80% with a misalignment tolerance of +/−15µm, optical cross talk is about −70dB. A silicon optical bench is fabricated as a platform for integrated photonic components. The thermal performance and electrical performance of optical sub-package is analyzed and optimized.