Tianmin Du

Accurate electrical simulation and design optimization for silicon interposer considering the MOS effect and eddy currents in the silicon substrate

In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. Simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.

A shielding structure with conductive adhesive coated on molding compound in 3D package

As electronic products tend to higher density, smaller area, lighter weight, and etc., three-dimensional (3D) packages are becoming effective chooses. Advanced 3D package technologies make the electronic products smaller with high density, but bring in more serious problems. The electromagnetic interference (EMI) is an important issue for more complex electromagnetic environment and smaller distance between noisy sources and sensitive circuits in the 3D package, especially in mixed signal system or RF/Microwave system. In this paper, a shielding structure with conductive adhesive covered on molding compound is researched. The shielding structure contains the molding compound, the conductive adhesive, and the ground plane and grounding vias. The conductive adhesive coated on the molding compound, and connects the ground plane or grounding vias on the top of substrate. To study the shielding performance, Device Under Tests (DUTs) are designed and fabricated in this paper. The test dies with Electro-Magnetic Coil are fabricated for DUTs to compare the isolation effect. The shielding performance of DUTs is measured by test system, which contains Vector Network Analyzer (VNA), coaxial cables and DUTs. The shielding efficiency (SE) of the novel structure is about 25dB below 8GHz, and the SE for high frequency is relative higher due to skin depth decreasing. The process of hybrid package with shielding structure is compatible with the normal package technology. The only additional step is the conductive adhesive coating. It is an effective method for suppressing near field noise in 3D mixed signal or RF/ Microwave package.

Fabrication and analysis of 2D embedded passive devices in PCB

This paper presents fabrication and electrical characterization of embedded passives in organic multilayered substrates. We have designed and fabricated a test board and a functional application focusing on embedded passives. A test board with two embedded capacitor layers and one embedded resistor layer was used to evaluate capacitance and resistance performance. The functional application was used to evaluate the performance of integrated passive devices (capacitors, resistors and inductors).

Design optimization and performance verification of multi-channel high-speed optical transceiver package

This article presents optic-electronic system on package, focus on signal integrity design optimization, and analysis method and performance verification of multi-channel two-way high-speed transceiver. Firstly the whole channel link performance is designed against all variables of interest. These variables are used to evaluate the solution at the system level. Signal integrity analysis and optimization of the high-density differential signal pairs on PCB is conducted to optimize impedance and minimize the effects of discontinuity in the electrical channels such as capacitor, via, connector.

A 9pJ/bit SOP optical transceiver with 80 Gbps two-way bandwidth

The high-speed parallel optical transmitter module based on VCSEL/PD array, high-speed specialized integrated circuit, fiber array micro-optical components presents magnificent application and development potential. The coupling alignment between VCSEL/PD array and waveguide array has been reported using silicon optical bench (SiOB) [1–3]. In this paper, A passive coupling method based on SiOB and the packaging of the VCSEL/PD arrays are introduced; the coupling efficiency is about 80% with a misalignment tolerance of +/−15µm, optical cross talk is about −70dB. A silicon optical bench is fabricated as a platform for integrated photonic components. The thermal performance and electrical performance of optical sub-package is analyzed and optimized.

Wideband noise isolation of planar EBG with embedded capacitors and inductors

This paper presents three related planar EBG (electromagnetic bandgap) structures based on embedded capacitors and inductors, which have small-footprints and can be used in package power or ground planes to provide wideband isolation among different parts of the power distribution network (PDN). Measurement shows -40dB isolation from 2-2.5GHz to over 10GHz. In order to improve performance at lower frequencies we explore the synthesis of planar EBG structures and Chip Ceramic Capacitors or Ferrite Beads.

A high-speed test board design for 40GHz Bandwidth die

It causes great challenge to the ordinary method to test the performance of the die when it comes to high frequency like 40GHz, especially for the optical die with some peripheral units, which causes extra difficulties with probes on the test bench. For the discontinuity of the impendence causes great loss for high-frequency signal, and it is difficult to place the die and the optical peripheral units on the test bench and to find a proper posture to conduct a precise experiment. A test board with a 3.5mm cable connector was designed to overcome these difficulties and to reduce the unnecessary loss caused in the test procedure. Dies connects to the test board via wire-bonding or flip chip. The trace/spacing changes from 70/30um to 880/560um. Considerable simulations were performed mainly for two purposes. Firstly, the model of 3.5mm connector and the connection with board was established in HFSS to search for the less discontinuities of the connector connecting to the board to reduce the loss in the process of the signal transmission. Secondly, the simulations of different trace design help to choose the route with less loss. Aside from the structure design, process and material and structure must be optimized to improve the performance of this package structure.

Design of test structures for electrical and reliability measurements in a 2.5D TSV interposer

A 2.5D three-dimensional (3D) silicon interposer with through silicon vias (TSV) was designed and fabricated. All structures are for the purpose of evaluating the design and layout, electrical testing, and to evaluate process reliability of the 2.5D interposer. Three levels are tested: chip, interposer and plastic substrate. The paper details the layout of the three levels, the principal electrical tests and extraction of TSV parameters such as the resistance of TSVs pads and lines. The design structure also tests the reliability of the 2.5D package structure by thermal stressing. The electrical test results are discussed in relation to applicability at high frequencies.

Optical vertical interconnect and integration based on Silicon carrier

This paper focuses on the research of optical vertical interconnect. To achieve optical vertical interconnect a new method for fiber plugging is introduced which also can be used for metal plugging. Because the pitch of both light spot of VCSEL array and sensitive surface of PD array is 250 um, and the pad pitch of VCSEL array and PD array are also 250um. So the pitch of V-Shape Groove or U -Shape Groove on silicon substrate is designed at 250um as a fixture for fiber or metal plugs. Many rows and columns of V-Shape Groove or U -Shape Groove can be stacked as a whole to finish metal wire or fiber plug and vertical distance of adjacent substrate is flexible according to application demand. After the fibers filled in the holes of a silicon interposer, the fiber is surrounded which is thermo curing material. The silicon interposer includes electrical transmission line and optical though silicon via (OTSV). VCSEL and PD assembled on Silicon carrier make up an optical block. Optical performance and microwave interconnect are discussed.

The development of wafer-level 3D high-density junction capacitor for passive device integration in SiP

Rapidly growing performance and mixed-signal integration is driving the requirement for product and component miniaturization in electronics applications. Embedded passive technology is a potentially attractive solution to replace discrete passives, due to low parasitic parameters, homogeneous integration and small form factor. Embedded capacitors are widely used in a broad range of applications including filtering, tuning and powerbus decoupling in the substrate. In this paper, Micro-Electron-Mechanical System (MEMS) process based on silicon 3D patterns etching and thermal diffusion doping of silicon is used to fabricate a high-density silicon-embedded capacitor. Deep 3D trench structures formed by the Bosch process in inductively coupled plasma (ICP) increase the effective capacitance area, thus enhancing the capacitance areal density. This paper reports on the fabrication process and electrical properties of silicon trench capacitors and achievable capacitance densities. Measurement results indicate that the 3D-structured capacitor can attain a capacitance density of 12nF/mm2, which is 10–12 times larger than that of planar semiconductor capacitors. This type of capacitor is a good candidate for high-power decoupling, filtering, and electrostatic discharge (ESD) protection, and may be preferred over SMT capacitors in electronics applications with form factor requirements.