Fengman Liu

Study on a Conformal Shielding Structure With Conductive Adhesive Coated on Molding Compound in 3-D Packages

With the continuous improvement of system integration, 3-D packages are becoming effective solutions for lighter, thinner, shorter, and smaller electronic products. Meanwhile, packaging engineers are faced with serious signal integrity challenges. Especially significant intrasystem electromagnetic interference (EMI) problems are aggravated for shortened distance between noise sources and sensitive circuits. In this paper, we present a conformal shielding structure with conductive adhesive coated on molding compound to improve the intrasystem EMI problems in 3-D packages. Three groups of die-stacking samples with different coupling mechanisms are fabricated to evaluate the shielding effectiveness. By comparing the noise isolation of the samples with and without shielding structures, we can clearly see the shielding capability of the conformal shielding structure. The measurement results indicate that the near field coupling noise isolation has significantly improved with the shielding structure. Compared with traditional methods, the conformal shielding structure can realize a cheaper, thinner, lighter, and more flexible shielding. It would be an effective shielding solution for suppressing near field radiation in 3-D mixed signal or RF/Microwave packages.

Thermal management of 3D RF PoP based on ceramic substrate

In this paper, a new high performance three dimensional radio frequency package on package (3D RF PoP) based on ceramic substrate is designed for micro base station which is able to cover the multicasting of critical messages to as many mobile users as possible even under communications network failure events, such as the failure of macro base stations. The RF PoP integrates receiver (RX) module, transmitter (TX) and digital predistortion (DPD) module, and analog-to-digital/digital-to-analog (AD/DA) and clock (CLK) module vertically, has better signal integrity and faster data-rate transfer due to shorter signal paths among the three modules. Additionally, the ceramic substrate has higher thermo-mechanical reliability and better heat dissipation performance compared with organic substrate. The paper firstly studies the thermal performance of the RF PoP without external heat sinks using commercial software ANSYS Icepak. At the ambient temperature of 25 °C, the highest junction temperature of the RF PoP is 239.8 °C, which is above the acceptable baseline for a silicon chip. Secondly, in order to improve the heat dissipation capability of the RF PoP, a large copper bottom heat dissipation plate is employed. The impact of bottom heat dissipation plate on the thermal performance of the RF PoP is investigated. It is found that a bottom heat dissipation plate of 200×200×2 mm3 is reasonable, and the highest junction temperature is about 47.0 °C. Thirdly, we study the thermal performance of the entire and internal package structure of the RF PoP mounted on the bottom heat dissipation plate. The temperature distributions of the top and middle substrates are almost uniform. Heat generated from active devices on the top and middle packages is mainly transferred to the edges, conducted to the bottom heat dissipation plate through the edges and bottom substrate and heat slug, heat generated from active devices on the bottom package is conducted to the bottom heat dissipation plate through the bottom substrate and heat slug, and then dissipated into the ambient by natural convection, so that the temperature at the edge of the bottom substrate is higher than the other parts. Lastly, the effect of different ambient temperatures on the thermal performance of the RF PoP is investigated. When the bottom heat dissipation plate size is 200×200×2 mm3 and the ambient temperature reaches 100 °C, the highest junction temperature is about 121 °C. In order to further improve heat dissipation capability of the RF PoP, a copper top heat spreader is employed. The simulation result shows that the junction temperature drops to about 115.6 °C.

Crosstalk analysis and optimization of high-speed interconnections

Crosstalk noise has become a major performance inhibitor in high speed digital system. This is especially the case in package designs, connector assemblies and circuit interconnects designs. With the simultaneous miniaturization of electronic systems and decreasing signal rise time, it is important to be able to predict major sources of crosstalk and to stay within the cross-talk budget for high-speed interconnects interfaces. In this paper, first, we focus on analyzing the crosstalk mechanism. Second, based on simulation, we propose methods to minimize crosstalk.

An electrical design and fabrication of a 12-channel optical transceiver with SiP packaging technology

This paper presents an electrical design of a 6.25Gbps×12-channel parallel optical transceiver with SiP packaging technology. Considering such high speed, a low impedance and low noise power distribution network (PDN) is designed to suppress simultaneous switching noise (SSN) and a novel embedded capacitor filter is used to replace the conventional power supply filter. To minimize the impedance discontinuity of electrical channels, a signal integrity (SI) design flow based on Electromagnetic Analysis Method and Circuit Analysis Method is proposed. Following this design flow, the high speed link performs on a large bandwidth. With the electrical design, the optical transceiver is fabricated and tested.

Thermal characterization of a novel 3D stacked package structure by CFD simulation

In this paper, a novel 3D stacked package structure with horizontal fins is designed to solve the heat dissipation issue. In order to verify the thermal performance, a 3D stacked package test vehicle with five chips and two interposers is built in a CFD software-Icepak. The size of the chip is in accordance with commercial thermal test chip (TTC-1002, TEA). Three different cooling methods of this architecture are studied, including natural convection, forced air convection, and immersion cooling. Temperature profiles under different external conditions are obtained and analyzed to determine the thermal resistances between adjacent chips qualitatively. Due to the increased heat flow paths, the novel 3D stacked package structure with horizontal fins has a better dissipation effect than traditional structure. The cooling capacity of immersion cooling is the best among the three cooling conditions. Through immersion cooling, the hot-spot temperature of this 3D stacked package can be maintained at a low level. The length of the fins is also studied to balance the optimal cooling performance and minimum volume occupancy. The length of the fins is very critical to the optimal cooling performance, especially in natural convection condition and forced air convection condition. The optimal length of the fin should be based on the heat dissipation of chips, the application environment, the reliability and also the costs. This work offers an insight look of thermal management for 3D stacked chips, and this structure is expected to be applied in future electronics.

A 10-Gbps × 12-Channel Pluggable Parallel Optical Transceiver Based on CXP Interface Specifications

Abstract A novel 10-Gbps × 12-channel pluggable parallel optical transceiver is designed and fabricated. Compared with other optical transceivers, this transceiver emphasizes small size, high-density, low power consumption, and high transmission speed. Most importantly, its optical coupling structure is simplified to promote cost-effective large-scale production. This transceiver is electrically pluggable and consists of transmitter and receiver modules linked by parallel multi-mode fibers. Each module consists of a six-layered high-speed, high-density printed circuit board, the size of which is 30 mm × 18 mm × 1 mm, packaged with optoelectronic devices and corresponding control chips. The printed circuit boards not only provide a high-speed electrical connection between the I/O interfaces and high-speed chips, but they also supply power and ground planes to those chips. End-to-end error-free transmission at 10.3125 Gbps was obtained for a 231 − 1 non-return-to-zero pseudo-random bit sequence.

Thermo-mechanical reliability analysis of a RF SiP module based on LTCC substrate

Abstract The RF SiP module based on LTCC substrate has attracted considerable attention in wireless communications for the last two decades. However, the thermo-mechanical reliability of this 3D LTCC architecture has not been well-studied as common as its traditional ceramic package structure. A practical RF SiP module based on LTCC substrate was presented and its thermo-mechanical reliability was analyzed in this paper, with emphasis on the reliability of heat reflow process, the operating state and fatigue of second-level solder joints. The configuration and assembly process of the SiP module were briefly introduced at first, and qualitative analysis was made according to the reliability problem that may occur in the manufacturing process and the operating state. Through FEM simulation, this paper studied the warpage and stress variation of the RF SiP module, as well as parametric studies of some key package dimensions. Solder joint reliability under temperature cycling condition was also analyzed in particular in this paper. The results show that for the heat reflow process and operating state, the maximum warpage is both on the top LTCC substrate, but the maximum stresses are on the outermost solder ball and the kovar column at the corner, respectively. There is a large residual stress on the critical solder ball at the end of the reflow process and the key package dimensions has little effect on it. The thickness of top LTCC substrate has a significant impact on the thermal deformation and thermal stress, followed by the height of kovar columns. The reason for the considerable thermal stress on the kovar column is the non-uniform of temperature distribution. The key to reducing thermal deformation and stress in the operating state is the employment of effective cooling measures. It is found by comparison that the reliability of critical solder joints can be greatly improved by adding suitable underfill.

Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package

Nowadays, fan-out package is regarded as one of the latest and most potential technologies because it possesses lower cost, thinner profile, and better electrical performance and thermal performance. However, thermally induced warpage in the molding process is a critical issue due to the larger wafer or panel size, the shrinkage of epoxy mold compound (EMC) during the curing stage, and the mismatch of coefficient of thermal expansion (CTE) among the constituent materials during the cooling stage, which needs to be controlled effectively for successful subsequent process of the fan-out package. In this paper, a novel

Parasitic parameter extraction and modeling of via of high speed differential pair

320 \times 320

Analysis on electromagnetic isolation issues among multi-chips in system in package

-mm2 panel-level fan-out package based on “Die Last” process is developed. A coreless substrate with redistribution layer is fabricated and bonded onto a low-CTE and high-glass-transition-temperature (Tg) FR4 carrier through thermal release film. The thermally induced warpage issue in the molding process is investigated. A warpage simulation method is presented and verified by Shadow Moiré experiment. The error between the simulation and experimental results is about 4.8%. For the warpage optimization analysis, the effect of geometry structure on the warpage is first investigated by the design of simulation approach. Full factor experiment is conducted, and Minitab statistical software is utilized to analyze the effect of the geometry structure on warpage. It is found that decreasing die thickness and molding thicker EMC can effectively decrease the warpage. Then, the effects of molding temperature and in-plane CTE of FR4 on warpage are studied, respectively. When molding temperature is 120 °C and in-plane CTE of FR4 decreases to 10.5 ppm/°C, the thermally induced warpage in the molding process is only about 0.31 mm, thus subsequent process of fan-out package can be conducted successfully.