Lixi Wan

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

Modeling of realistic on-chip power grid using the FDTD method

In this paper, a multi-layered on-chip power distribution network has been modeled using the finite difference time domain (FDTD) method. This simulation consists of 0.5 million passive elements, 40000 distributed current sources and multiple C4 vias. In this method, a branch capacitor has been used, which is different from latency insertion method (LIM). The use of the branch capacitor is important for simulating multi-layered power grids. The current in the branch capacitor is extracted from Kirchhoffs current law. This provides a good model of the branch capacitor and does not require companion models during simulation. The proposed model has been verified with SPICE through a simple example. The on-chip power grid simulation, the characteristics of noise propagation and the effectiveness of on-chip decoupling capacitors have been discussed. Also the importance of the nonlinearity in the computation of the power supply noise in on- chip power grid has been addressed through the peak noise analysis using linear current source and clock distribution network.

Magnetic nanocomposites for organic compatible miniaturized antennas and inductors

Current wireless systems are limited by RF technologies in their size, communication range, efficiency and cost. RF circuits are difficult to miniaturize without compromising performance. Antennas and inductors are major impediments for system miniaturization because of the lack of magnetic materials with suitable high frequency properties. Keeping antenna and inductor requirements into consideration, two magnetic nanocomposite systems - silica coated cobalt-BCB and Ni ferrite-epoxy were investigated as candidate materials. Nanocomposite thick film structures (125-225 microns) were screen printed onto organic substrates. Parallel plate capacitors and single coil coplanar inductors were fabricated on these films to characterize the electrical and magnetic properties of these materials at low and high frequencies. Electrical characterization showed that the Co/SiO/sub 2/ nanocomposite sample has a permeability and a matching permittivity of /spl sim/10 at GHz frequency range making it a good antenna candidate. Both polymer matrix composites retain high permeability at 1-2 GHz.

Embedded decoupling capacitor performance in high speed circuits

Embedded decoupling is normally considered a better solution than surface mount decoupling for suppressing the switching noise of a high speed digital board/package because of its shorter leads that result in smaller parasitic inductance. This leads to lower impedance over a higher frequency band. It is presumably better in reliability and lowers the cost as well. Designers tend to use large value capacitors for efficient decoupling. Usually, to increase capacitance of an embedded capacitor, one can use a material with higher dielectric constant, design larger electrodes, and reduce the thickness of the dielectric. However, these strategies may sometimes lead to lower performance at high frequency band. This paper will discuss the pros and cons of different embedded capacitor approaches through simulation. As an application example, a typical power/ground network with an embedded capacitor will be compared with that of surface mount discrete capacitor.

Design, modeling and characterization of embedded capacitor networks for mid-frequency decoupling in semiconductor systems

Embedded passives are gaining in importance due to the reduction in size of consumer electronic products. Among the passives, capacitors pose the biggest challenge due to the large capacitance required for decoupling high performance circuits. This paper focuses on the characterization and modeling of embedded capacitors. Design and modeling of embedded capacitor networks for decoupling semiconductor systems in the mid-frequency band (100 MHz to 2 GHz) will be highlighted in this paper

Design, simulation and measurement techniques for embedded decoupling capacitors in multi-GHz packages/PCBs

Embedded capacitor is a better solution than surface mount capacitors for decoupling in a high speed, high performance packages/PCBs. Our study has showed that with conventional approaches, the embedded capacitor for decoupling in power delivering network can work from 100 MHz to 1 GHz systems. Pushing the operating frequency over 1 GHz is a challenge for system designers. This paper discusses the embedded decoupling capacitor design for multi-GHz systems through principles, simulation, measurement error, and error elimination.

Simultaneous switching noise suppression using hydrothermal barium titanate thin film capacitors

This paper reports the integration of hydrothermal barium titanate thin film embedded capacitors in organic printed wiring boards. These capacitors have 300 nm thick dielectrics with k>350, can attain capacitances of 1 /spl mu/F/cm/sup 2/ and are ideal for decoupling applications. In order to evaluate these films for simultaneous switching noise suppression, a clock distribution network was designed using a clock driver with one input and four differential outputs. The design consists of a clock driver and four pairs of impedance controlled transmission lines with embedded decoupling capacitors. In order to evaluate the effects of capacitance value and the type of capacitor /sub i/screte vs. embedded, coupons with different embedded capacitance values and discrete capacitors were fabricated on the same board. The fabricated structures were simulated using the transmission matrix method (TMM) in the frequency domain and a macromodeling method in the time domain. This paper demonstrates for the first time that the simple low-cost, aqueous based low-temperature film growth technique can provide the best solution for embedded decoupling capacitor problems in organic packages.

Packaging of multi-core microprocessors: tradeoffs and potential solutions

Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multicore processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade offs between single and multicore processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.

System-on-a-package (SOP) substrate and module with digital, RF and optical integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, and optical system integration on a single package. SOP aims to utilize the best of on-chip SOC integration and package integration to achieve the highest system performance at the lowest cost. The micro-miniaturized multi-functional SOP package is highly integrated and fabricated on large area substrates similar to the wafer-to-IC concept. In addition to novel mixed signal design methodologies, SOP research at PRC is targeted at developing enabling technologies for package level integration including ultra-high density wiring, embedded passive components, embedded optical interconnects, wafer level packaging and fine pitch assembly. Several of these enabling technologies have been recently integrated into the first successful system level demonstration of SOP technology using the intelligent network communicator (INC) testbed. This paper reports on the latest INC and SOP testbed results at the PRC and provides an insight into the future SOP integration strategy for convergent microsystems. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation.

Board-level optical-to-electrical signal distribution at 10 gb/s

An opto/electrical prototype for on-board optical-to-electrical signal broadcasting operating at 10 Gb/s per channel over an interconnect distance of 10 cm is demonstrated. An improved 1times4 multimode interference (MMI) splitter at 1550 nm with linearly tapered output facet is heterogeneously integrated with four p-i-n photodetectors (PDs) on a silicon (Si) bench. The Si bench itself is hybrid integrated onto an FR-4 printed-circuit board with four receiver channels. A novel fabrication/integration approach demonstrates the simultaneous alignment between the four waveguides and the four PDs during the MMI fabrication process. The entire system is fully functional at 10 Gb/s