Bastien Douhard

Undoped and in-situ B doped GeSn epitaxial growth on Ge by atmospheric pressure-chemical vapor deposition

In this letter, we propose an atmospheric pressure-chemical vapor deposition technique to grow metastable GeSn epitaxial layers on Ge. We report the growth of defect free fully strained undoped and in-situ B doped GeSn layers on Ge substrates with Sn contents up to 8%. Those metastable layers stay fully strained after 30 min anneal in N2 at 500 °C; Ge-Sn interdiffusion is seen at 500 °C but not at lower temperature. B is 100% active in the in-situ GeSn:B layers up to a concentration of 1.7 × 1019 cm−3. GeSn:B provides slightly lower Hall hole mobility values than in pure p-type Ge especially for low B concentrations.

Contact resistivity and Fermi-level pinning in n-type Ge contacts with epitaxial Si-passivation

We report on the study of the electrical and material properties of n-Ge contacts with a thin Si-passivation layer. n-Ge contacts typically show Fermi-level pinning and low dopant activation which results in too large specific contact resistivities of >10−4 Ω cm2 and which impedes applications such as high performance Ge complementary metal-oxide semiconductor technology. In this work a thin in situ doped (1×1020 cm−3 of phosphorus) epitaxial Si-passivation layer is grown selectively on n-Ge, followed by a Ti/TiN stack deposition. The insertion of this thin Si-passivation layer reduces the pinning and activation limitation, achieving specific contact resistivity values of ∼1×10−6 Ω cm2. Physical modeling of the specific contact resistivities was performed, providing the insight validating the underlying explanation of the improvement. Key factors for the contact resistivity lowering are the good alignment of the Si and Ge conduction bands and the higher doping concentration achieved in Si.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual...

GeSn channel nMOSFETs: Material potential and technological outlook

Semiconducting germanium tin (GeSn) alloy has recently emerged as a candidate for optoelectronic and high performance CMOS devices because of its tunable direct gap and potential for high electron and hole mobilities. High hole mobility in GeSn channel pMOSFETs has already been demonstrated [1, 2]. However, GeSn as channel for nMOSFETs has not yet been explored. In this work we perform detailed theoretical analysis to gauge the benefits of GeSn channel over Ge for nMOSFETs. Our analysis predicts GeSn nMOSFETs to outperform Ge. GeSn n-channel devices have been successfully fabricated and factors limiting its performance.

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Field Effect and Strongly Localized Carriers in the Metal-Insulator Transition Material VO(2).

The intrinsic field effect, the change in surface conductance with an applied transverse electric field, of prototypal strongly correlated VO(2) has remained elusive. Here we report its measurement enabled by epitaxial VO(2) and atomic layer deposited high-κ dielectrics. Oxygen migration, joule heating, and the linked field-induced phase transition are precluded. The field effect can be understood in terms of field-induced carriers with densities up to ∼5×10(13)  cm(-2) which are trongly localized, as shown by their low, thermally activated mobility (∼1×10(-3)  cm(2)/V s at 300 K). These carriers show behavior consistent with that of Holstein polarons and strongly impact the (opto)electronics of VO(2).

Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors

Band-to-band tunneling parameters of strained indirect bandgap materials are not well-known, hampering the reliability of performance predictions of tunneling devices based on these materials. The nonlocal band-to-band tunneling model for compressively strained SiGe is calibrated based on a comparison of strained SiGe p-i-n tunneling diode measurements and doping-profile-based diode simulations. Dopant and Ge profiles of the diodes are determined by secondary ion mass spectrometry and capacitance-voltage measurements. Theoretical parameters of the band-to-band tunneling model are calculated based on strain-dependent properties such as bandgap, phonon energy, deformation-potential-based electron-phonon coupling, and hole effective masses of strained SiGe. The latter is determined with a 6-band k·p model. The calibration indicates an underestimation of the theoretical electron-phonon coupling with nearly an order of magnitude. Prospects of compressively strained SiGe tunneling transistors are made by simulations with the calibrated model.

Boron Delta-Doping Dependence on Si/SiGe Resonant Interband Tunneling Diodes Grown by Chemical Vapor Deposition

Si/SiGe resonant interband tunnel diodes (RITD) were fabricated using CVD on 200-mm silicon wafers. The RITD devices consist of a p+-i-n+ structure with δ-doped quantum wells providing resonant interband tunneling through a nominally intrinsic Si/SiGe region. The vapor-phase doping technique was used to obtain abrupt degenerate doping profiles. The boron doping in the δ-doped region was varied, and its effect on peak current density Jp and peak-to-valley current ratio (PVCR) was studied. As the flow rate is reduced, Jp was found to reduce while the PVCR initially increases and then decreases. Device simulations were performed using the ATLAS simulator developed by SILVACO to interpret the results. A maximum PVCR of 2.95 was obtained, and the highest Jp recorded was 600 A/cm2. This is the highest reported PVCR for any CVD-grown Si/SiGe RITD.

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10-10 A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.