Alain Moussa

Experimental studies of dose retention and activation in fin field-effect-transistor-based structures

With emerging three-dimensional device architectures for advanced silicon devices such as fin field-effect-transistors (FinFETs), new metrology challenges are faced to characterize dopants. The ratio of dopant concentration in the top surface and sidewalls of FinFETs may differ significantly, thereby influencing the performance of these devices. In this work, a methodology involving secondary ion mass spectrometry (SIMS) is presented to study the dose conformality in fins. However, SIMS is limited to probe the quantitative chemical dopant concentration (i.e., top/sidewall of fins). The fraction of the active dopant concentration determining the performance of FinFETs would still be unknown. Additionally, the concept based on SIMS is unable to provide information on the lateral junction depth. Thus, to obtain the unknown active dopant concentration and their spatial distribution, the authors extend their study by measuring the cross section of the fins with scanning spreading resistance microscopy and extracting the quantitative active carrier concentration in the fins.With emerging three-dimensional device architectures for advanced silicon devices such as fin field-effect-transistors (FinFETs), new metrology challenges are faced to characterize dopants. The ratio of dopant concentration in the top surface and sidewalls of FinFETs may differ significantly, thereby influencing the performance of these devices. In this work, a methodology involving secondary ion mass spectrometry (SIMS) is presented to study the dose conformality in fins. However, SIMS is limited to probe the quantitative chemical dopant concentration (i.e., top/sidewall of fins). The fraction of the active dopant concentration determining the performance of FinFETs would still be unknown. Additionally, the concept based on SIMS is unable to provide information on the lateral junction depth. Thus, to obtain the unknown active dopant concentration and their spatial distribution, the authors extend their study by measuring the cross section of the fins with scanning spreading resistance microscopy and extr...

Impact of thermal treatment upon morphology and crystallinity of strontium titanate films deposited by atomic layer deposition

Strontium titanate (STO) is a dielectric with a cubic perovskite type structure and of increasing interest for microelectronics, especially in the metal-insulator-metal (MIM) capacitors due to its high dielectric constant. The dielectric constant of the STO films and consequently the performance of the MIM capacitors appear to be strongly influenced by the process conditions. In this work the authors report on the influence of various thermal treatments upon the crystallinity and morphology of strontium titanate crystals. The influence of spike, laser, or rapid thermal anneals on the morphology with respect to grain size and topography of the crystalline stoichiometric STO films is studied. Also, the use of a stack containing a Sr-rich STO (62% Sr) bottom seed layer and a stoichiometric STO top layer in combination with a thermal treatment was found to affect the microstructure of the STO film. A comparison of the electrical properties for various thermal treatments has been made.

Roughness evolution during the atomic layer deposition of metal oxides

The evolution of the surface roughness during the atomic-layer deposition (ALD) of Al2O3, NiO, and HfO2 was studied by atomic-force microscopy and nonspecular x-ray reflectance. The results indicate that the crystallinity of the films played a crucial role in the roughness evolution during ALD. While the ALD of amorphous oxide films showed replication of the initial starting surface with no roughness build-up, the ALD of polycrystalline oxide films led to a strong anomalous dependence of the roughness on the film thickness. This behavior is explained within a model taking into account spatial variations of the adsorption site density.

Ultrathin NiGe Films Prepared via Catalytic Solid–Vapor Reaction of Ni with GeH4

A low-temperature (225-300 °C) solid-vapor reaction process is reported for the synthesis of ultrathin NiGe films (∼6-23 nm) on 300 mm Si wafers covered with thermal oxide. The films were prepared via catalytic chemical vapor reaction of germane (GeH4) gas with physical vapor deposited (PVD) Ni films of different thickness (2-10 nm). The process optimization by investigating GeH4 partial pressure, reaction temperature, and time shows that low resistive, stoichiometric, and phase pure NiGe films can be formed within a broad window. NiGe films crystallized in an orthorhombic structure and were found to exhibit a smooth morphology with homogeneous composition as evidenced by glancing angle X-ray diffraction (GIXRD), scanning electron microscopy (SEM), atomic force microscopy (AFM), and Rutherford back-scattering (RBS) analysis. Transmission electron microscopy (TEM) analysis shows that the NiGe layers exhibit a good adhesion without voids and a sharp interface on the thermal oxide. The NiGe films were found to be morphologically and structurally stable up to 500 °C and exhibit a resistivity value of 29 μΩ cm for 10 nm NiGe films.

Photovoltage versus microprobe sheet resistance measurements on ultrashallow structures

Earlier work [T. Clarysse et al., Mater. Sci. Eng., B 114–115, 166 (2004); T. Clarysse et al., Mater. Res. Soc. Symp. Proc. 912, 197 (2006)] has shown that only few contemporary tools are able to measure reliably (within the international technology roadmap for semiconductors specifications) sheet resistances on ultrashallow (sub-50-nm) chemical-vapor-deposited layers [T. Clarysse et al., Mater. Res. Soc. Symp. Proc. 912, 197 (2006)], especially in the presence of medium/highly doped underlying layers (representative for well/halo implants). Here the authors examine more closely the sheet resistance anomalies which have recently been observed between junction photovoltage (JPV) based tools and a micrometer-resolution four-point probe (M4PP) tool on a variety of difficult, state-of-the-art sub-32-nm complementary metal-oxide semiconductor structures (low energy and cluster implants, with/without halo, flash- and laser-based millisecond anneal). Conventional four-point probe tools fail on almost all of thes...

Wet Chemical Cleaning of InP and InGaAs

In this work, the compatibility of InP and InGaAs in cleaning solutions commonly used in semiconductor manufacturing is investigated. Aqueous oxidizing cleans should be avoided as the substrates dissolve rapidly. Low pH solutions may impose some serious ES&H issues due to hydride evolution occurring upon acidic hydrolysis of the III-V material. However, acidic solutions are very efficient to remove the native oxide from the substrate. Complete oxide free surfaces are not achieved after wet cleaning due to the rapid oxidation of these materials in the atmosphere.

Insights in junction photovoltage based sheet resistance measurements for advanced complementary metal-oxide semiconductor

Earlier work has clearly shown that only a very few tools are able to measure reliably sheet resistances on advanced complementary metal-oxide semiconductor (CMOS) structures. One of these promising techniques is the junction photovoltage based technique, which uses a modulated light emitting diode to generate, in a millimeter size area of a single junction isolated structure, excess carriers which are separated by the underlying electrical field, and subsequently outdiffuse laterally. From the lateral variation in junction photovoltage, one can extract in a noncontact way the sheet resistance (Rs) of the top layer and the junction leakage (L) of the junction. First, a simplified theoretical solution of the underlying diffusion equations will be presented. Next, a recently developed simulation framework will be discussed, combining the SCILAB environment with SYNOPSIS∕MEDICI device simulations, allowing for the detailed study of both ideal (in agreement with the theoretical solution) and less ideal advanc...

Selective Epitaxy of Si/SiGe to improve pMOS devices by recessed Source/Drain and/or Buried SiGe Channels

SiGe R. Loo, P. Verheyen, R. Rooyackers, C. Walczyk*, F.E. Leys, D. Shamiryan, P.P. Absil, T. Delande, A. Moussa, J.W. Weijtmans, R. Wise, V. Machkaoutsan, C. Arena, J. McCormack, S. Passefort, H. Sorada, A. Inoue, B.C. Lee, S. Hyun, S. Jakschik, and M. Caymax 1 IMEC, Kapeldreef 75, 3001 Leuven (Belgium), *also Universitat Siegen, Holderlinstrasse 35, 7068 Siegen (Germany), Texas Instruments Inc., 13560 North Central Expressway, Dallas (USA), ASM-Belgium, Kapeldreef 75, 3001 Leuven (Belgium), ASM-America, 3440 East University Drive, Phoenix, (USA), KLA-Tencor Corp. 160 Rio Robles, San Jose (USA), Matsushita assignee at IMEC, Samsung assignee at IMEC, Infineon assignee at IMEC

The need for LWR metrology standardization: the imec roughness protocol

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Surface characterization of InP trenches embedded in oxide using scanning probe microscopy

Metrology for structural and electrical analyses at device level has been identified as one of the major challenges to be resolved for the sub-14u2009nm technology nodes. In these advanced nodes, new high mobility semiconductors, such as III–V compounds, are grown in narrow trenches on a Si substrate. Probing the nature of the defects, the defect density, and the role of processing steps on the surface of such structures are prime metrology requirements. In order to enable defect analysis on a (III–V) surface, a proper sample preparation for oxide removal is of primary importance. In this work, the effectiveness of different chemical cleanings and thermal annealing procedures is investigated on both blanket InP and oxide embedded InP trenches by means of scanning probe microscopy techniques. It is found that the most effective approach is a combination of an HCl-based chemical cleaning combined with a low-temperature thermal annealing leading to an oxide free surface with atomically flat areas. Scanning tunne...