Baylor B. Triplett

Germanium MOS capacitors incorporating ultrathin high-/spl kappa/ gate dielectric

For the first time, we have successfully demonstrated the feasibility of integrating a high-permittivity (/spl kappa/) gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates. The entire fabrication process was essentially performed at room temperature with the exception of a 410/spl deg/C forming gas anneal. After processing steps intended to remove the germanium native oxide interlayer between the zirconium oxide dielectric and germanium substrate, an excellent capacitance-based equivalent SiO/sub 2/ thickness (EOT) on the order of 5-8 /spl Aring/ and capacitance-voltage (C-V) characteristics with hysteresis of 16 mV have been achieved. Additionally, excellent device yield and uniformity were possible using this low thermal budget process.

Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10−5 A/cm2 at a bias of −1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8–10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ∼3×1011 states/cm eV wa...

A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate

A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.

Thermal stability of polycrystalline silicon electrodes on ZrO2 gate dielectrics

Thermal stability of gate stack structures composed of ZrO2 gate dielectrics and silicon electrodes was investigated. The ZrO2 films were deposited by atomic layer deposition, while the polycrystalline silicon electrodes were deposited using different variants of chemical (CVD) and physical vapor deposition (PVD). Zirconium silicide formation was noted in all CVD-electroded samples after subsequent annealing treatments at temperatures above 750 °C, but not in the room temperature PVD-electroded samples, even after gate annealing at 1050 °C. The dependence of zirconium silicide formation on the Si deposition process was explained using thermodynamic arguments which explicitly include the effects of oxygen deficiency of the metal oxide films.

Zirconia grown by ultraviolet ozone oxidation on germanium (100) substrates

Growth of zirconia (ZrO2)-based gate dielectrics on germanium (Ge) substrates by oxidation using activated oxygen species produced by ultraviolet radiation (UV/ozone) is reported here. In this technique, a thin layer of zirconium (Zr) metal (10–30 A) is deposited by physical vapor deposition on Ge and subsequently oxidized in reactive oxygen. X-ray photoelectron spectroscopy (XPS) analysis indicates complete oxidation of the Zr metal. High resolution transmission electron microscopy (TEM) of UV-ozone oxidized ZrO2 on Ge indicates a sharp interface between the oxide and the substrate. However, conventional TEM is not well suited for identifying a Ge oxide layer in this system due to the closeness in atomic number of Zr and Ge. XPS spectra suggest the presence of a substoichiometric Ge oxide phase at the ZrO2/Ge interface. Depth profiling using angle-resolved XPS was performed on ZrO2/Ge gate stacks of varying oxide thickness. The results indicate that the amount of Ge oxide is dependent upon the ZrO2 overl...

Electron spin resonance study of as-deposited and annealed (HfO2)x(SiO2)1−x high-κ dielectrics on Si

Electron spin resonance measurements on 4 and 40nm thick (HfO2)0.6(SiO2)0.4 and (HfO2)0.4(SiO2)0.6 high-κ films on (100)Si wafers detected Pb0 and Pb1 defects at the dielectric/Si interface and verified their identities with g value mapping. Annealings of a 4nm thick (HfO2)0.6(SiO2)0.4 film in nitrogen at 800 and 1000°C monotonically lowered total interface states. In contrast, the same annealings monotonically increased the total interface states observed in 40nm thick films of both compositions. For the 4nm technologically relevant thickness, the annealed (HfO2)0.6(SiO2)0.4 composition on (100)Si had lower interface states than the (HfO2)0.4(SiO2)0.6 composition on (100)Si. After nitrogen annealing at 800°C, a third defect believed to be the EX, appears in larger quantities in the thicker 40nm films.

Ultrathin high-/spl kappa/ gate dielectric technology for germanium MOS applications

For the first time, we have successfully demonstrated the use of a high-/spl kappa/ gate dielectric material, ZrO/sub 2/, for CMOS applications on a pure germanium substrate. Using a low-temperature formation technique, we achieved excellent C-V characteristics with hysteresis of 1.5 mV and a capacitance-based equivalent SiO/sub 2/ thickness (t/sub ox,eq/) of about 5 /spl Aring/. Additionally, excellent device uniformity and very high device yield were attained.

Analysis of electrically biased paramagnetic defect centers in HfO2 and HfxSi1−xO2/(100)Si interfaces

This study reports on the first experimental observations of electrically biased paramagnetic defects at 800 °C N2 annealed HfxSi1−xO2 (x=0.4, and 0.6)/(100)Si and HfO2/(100)Si interfaces in metal oxide silicon structures. These defects are examined by electrical-field controlled electron spin resonance (ESR) and correlated with capacitance-voltage (C-V) analysis. Distributions of ESR measured density of interface traps (ESR-Dit), Pb0 and Pb1, exhibit distinct charge humps and peaks in the Si bandgap with maximum defect density of 0.9–1.9×1012 cm−2 eV−1 in the Hf0.4Si0.6O2/Si interface. Three Pb0 and one Pb1 charged ESR-Dit peaks with density of 1.7–2.8×1012 cm−2 eV−1 are observed in the Hf0.6Si0.4O2/Si interface. Cross-sectional transmission electron microscopic images show decreasing interfacial layer (IL) thickness with increasing hafnium composition (x) at the HfxSi1−xO2/Si interface. The roughest IL observed at the HfO2/Si interface may have contributed to an ESR-Dit of Pb0 greater than 2×1013 cm−2 e...

A novel self-aligned gate-lost MOSFET process comparing high-/spl kappa/ candidates

In this paper the two metal oxide dielectrics (ZrO/sub 2/ and HfO/sub 2/) deposited in the same chamber with the same technique using a newly developed self-aligned gate-last MOSFET process are compared. The compared results suggested that using either ZrO/sub 2/ or HfO/sub 2/ would provide similar on-to-off current ratio at a given device size.