Benjamin Belzer

Wavelet filter evaluation for image compression

Choice of filter bank in wavelet compression is a critical issue that affects image quality as well as system design. Although regularity is sometimes used in filter evaluation, its success at predicting compression performance is only partial. A more reliable evaluation can be obtained by considering an L-level synthesis/analysis system as a single-input, single-output, linear shift-variant system with a response that varies according to the input location module (2(L),2(L)). By characterizing a filter bank according to its impulse response and step response in addition to regularity, we obtain reliable and relevant (for image coding) filter evaluation metrics. Using this approach, we have evaluated all possible reasonably short (less than 36 taps in the synthesis/analysis pair) minimum-order biorthogonal wavelet filter banks. Of this group of over 4300 candidate filter banks, we have selected and present here the filters best suited to image compression. While some of these filters have been published previously, others are new and have properties that make them attractive in system design.

Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems

Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing demand for low-power and high-speed interconnects with technology scaling necessitates looking beyond the conventional planar metal/dielectric-based interconnect infrastructures. Among different possible alternatives, the on-chip wireless communication network is envisioned as a revolutionary methodology, capable of bringing significant performance gains for multicore SoCs. Wireless NoCs (WiNoCs) can be designed by using miniaturized on-chip antennas as an enabling technology. In this paper, we present design methodologies and technology requirements for scalable WiNoC architectures and evaluate their performance. It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude. The performance of the proposed WiNoC is evaluated in presence of various traffic patterns and also compared with other emerging alternative NoCs.

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Current commercial systems-on-chips (SoCs) designs integrate an increasingly large number of predesigned cores and their number is predicted to increase significantly in the near future. For example, molecular-scale computing promises single or even multiple order-of-magnitude improvements in device densities. The network-on-chip (NoC) is an enabling technology for integration of large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of long multi-hop links used in data exchange. The latency, power consumption and interconnect routing problems of conventional NoCs can be addressed by replacing or augmenting multi-hop wired paths with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper, we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.

Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects

The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.

Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects

Network-on-chip (NOC) is emerging as a revolutionary methodology to integrate numerous intellectual property blocks in a single die. It is the packet switching-based communications backbone that interconnects the components on multicore system-on-chip (SoC). A major challenge that NOC design is expected to face is related to the intrinsic unreliability of the interconnect infrastructure under technology limitations. By incorporating error control coding schemes along the interconnects, NOC architectures are able to provide correct functionality in the presence of different sources of transient noise and yet have lower overall energy dissipation. In this paper, designs of novel joint crosstalk avoidance and triple-error-correction/quadruple-error-detection codes are proposed, and their performance is evaluated in different NOC fabrics. It is demonstrated that the proposed codes outperform other existing coding schemes in making NOC fabrics reliable and energy efficient, with lower latency.

Filter evaluation and selection in wavelet image compression

Choice of filter bank in wavelet compression is a critical issue that affects image quality as well as system design. Although regularity is sometimes used in filter evaluation, its success at predicting compression performance is only partial. A more reliable evaluation can be obtained by considering an L-level synthesis/analysis system as a single-input, single-output, linear shift-variant system with a response that varies according to the input location modulo (2/sup L/, 2/sup L/). By characterizing a filter bank according to its impulse response and step response in addition to regularity, the authors obtain reliable and relevant (for image coding) filter evaluation metrics. Using this approach, they have evaluated all possible reasonably short (less than 34 taps in the synthesis/analysis pair) minimum order biorthogonal wavelet filter banks. Of this group of over 4300 candidate filter banks, they have selected and presented the filters best suited to image compression. While some of these filters have been published previously, others are new and have properties that make them attractive in system design.<<ETX>>

Performance evaluation and design trade-offs for wireless network-on-chip architectures

Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.

Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding

With the ever-increasing degrees of integration, design of communication architectures for big systems on chip (SoCs) is a challenge. The communication requirements of these large multi processor SoCs (MP-SoCs) are convened by the emerging network-on-a-chip (NoC) paradigm. To become a viable alternative IC design methodology, the NoC paradigm must address system-level reliability issues, which are among the dominant concerns for SoC design. The basic operations of NoCs are governed by on-chip packet switched networks. On the other hand, incorporation of different coding schemes in SoC design is being investigated as a means to increase system reliability. As NoCs are built on packet-switching, it is very natural to modify the data packets by adding extra bits of coded information to protect against any transient malfunction. By incorporating joint crosstalk avoidance coding (CAC) and forward error correction (FEC) schemes in the NoC data stream we are able to enhance the system reliability and at the same time reduce communication energy

Row-Column Soft-Decision Feedback Algorithm for Two-Dimensional Intersymbol Interference

We present a novel iterative row-column soft decision feedback algorithm (IRCSDFA) for detection of binary images corrupted by 2-D intersymbol interference and additive white Gaussian noise. The algorithm exchanges weighted soft information between row and column maximum a posteriori (MAP) detectors. Each MAP detector exploits soft-decision feedback from previously processed rows or columns. The new algorithm gains about 0.3 dB over the previously best published results for the 2times2 averaging mask. For a non-separable 3times3 mask, the IRCSDFA gains 0.8 dB over a previous soft-input/soft-output iterative algorithm which decomposes the 2-D convolution into 1-D row and column operations.

Adaptive video coding for mobile wireless networks

Wireless video transmission over a dynamic network requires adaptation to changes in bandwidth, network traffic, and channel characteristics. New computing hardware and algorithms are needed that enable low-power, flexible, adaptive, and robust video communication in hostile environments with no access to an installed communications infrastructure. The coding algorithms we are developing are based on subband decomposition using integer-coefficient filters, and adaptively deliver video at rates between 60 kbits/sec and 600 kbits/sec in accordance with the available bandwidth. Robustness in the variable length coder is obtained by using low-overhead Reed-Solomon block codes, by performing intra-frame coding only, and by using end-of-frame and end-of-subband symbols to maintain both inter- and intra-frame synchronization.<<ETX>>