David Goren

A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control

A + 20 dBm power amplifier (PA) for applications in the 60 GHz industrial scientific medical (ISM) band is presented. The PA is fabricated in a 0.13-mum SiGe BiCMOS process technology and features a fully-integrated on-chip RMS power detector for automatic level control (ALC), built-in self test and voltage standing wave ratio (VSWR) protection. The single-stage push-pull amplifier uses center-tapped microstrips for a highly efficient and compact layout with a core area of 0.075 mm2. The PA can deliver up to 20 dBm, which to date, is the highest reported output power at mm-wave frequencies in silicon without the need for power combining. At 60 GHz it achieves a peak power gain of 18 dB, a 1-dB compression (P1dB) of 13.1 dBm, and a peak power-added efficiency (PAE) of 12.7%. The amplifier is programmable through a three-wire serial digital interface enabeling an adaptive bias control from a 4-V supply.

A 23-dBm 60-GHz Distributed Active Transformer in a Silicon Process Technology

In this paper, a distributed active transformer for the operation in the millimeter-wave frequency range is presented. The transformer utilizes stacked coupled wires as opposed to slab inductors to achieve a high coupling factor of kf=0.8 at 60 GHz. Scalable and compact equivalent-circuit models are used for the transformer design without the need for full-wave electromagnetic simulations. To demonstrate the feasibility of the millimeter-wave transformer, a 200-mW (23 dBm) 60-GHz power amplifier has been implemented in a standard 130-nm SiGe process technology, which, to date, is the highest reported output power in an SiGe process technology at millimeter-wave frequencies. The size of the output transformer is only 160times160 mum2 and demonstrates the feasibility of efficient power combining and impedance transformation at millimeter-wave frequencies. The two-stage amplifier has 13 dB of compressed gain and achieves a power-added efficiency of 6.4% while combining the power of eight cascode amplifiers into a differential 100-Omega load. The amplifier supply voltage is 4 V with a quiescent current consumption of 300 mA

Compact Modeling and Comparative Analysis of Silicon-Chip Slow-Wave Transmission Lines With Slotted Bottom Metal Ground Planes

A compact modeling approach for silicon-chip slow-wave transmission lines with slotted bottom metal ground planes is studied and its limitations are presented. The modeling approach facilitates the calculation of the slow-wave transmission line parameters based upon the corresponding coplanar and grounded coplanar transmission-line parameters. The described analysis method is used for a comparative study of the slow-wave structures versus their coplanar and grounded coplanar reference structures. Floating bottom shield slow-wave transmission lines are then compared with their grounded bottom shield counterparts. The theoretical results are supported by electromagnetic simulations and by measurements up to 30 and 50 GHz.

On-chip SiGe transmission line measurements and model verification up to 110 GHz

On-chip microstrip transmission lines have been measured on-wafer from below 1 GHz up to 110 GHz. Using different pad de-embedding techniques as well as a technique based on two transmission lines of different length, the characteristic transmission line parameters have been accurately determined. The results are compared against simulation results from an electromagnetic full-wave solution and the parametric IBM model which is available in the technologys design kit.

On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices

This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in D. Goren et al. (2002), into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T-line) devices for the critical interconnects, which is expanded to include coplanar structures while considering the silicon substrate effect. The generalized methodology contains treatment of the crossing line effects at the various design stages, including two way interactions between the post layout extraction tool and the T-line devices. The T-line device models are passive by construction, easily migratable among design environments, and allow for both time and frequency domain simulations. These models are verified by S-parameter measurements up to 110GHz, as well as by EM solver results. It is experimentally shown that the effect of properly designed discontinuities is negligible in most practical cases. The basic on-chip T-line methodology is being used extensively for numerous high-speed designs.

An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach

This paper presents an on-chip, interconnect-aware methodology for high-speed analog and mixed signal (AMS) design which enables early incorporation of on-chip transmission line (T-line) components into AMS design flow. The proposed solution is based on a set of parameterized T-line structures, which include single and two coupled microstrip lines with optional side shielding, accompanied by compact true transient models. The models account for frequency dependent skin and proximity effects, while maintaining passivity requirements due to their pure RLC nature. The signal bandwidth supported by the models covers a range from DC to 100 GHz. The models are currently verified in terms of S-parameter data against hardware (up to 40 GHz) and against EM solver (up to 100 GHz). This methodology has already been used for several designs implemented in SiGe (silicon-germanium) BiCMOS technology.

SiGe transformer matched power amplifier for operation at millimeter-wave frequencies

In this paper, a transformer matched power amplifier for operation at millimeter-wave frequencies is presented. The SiGe single-stage push-pull amplifier uses a stacked transformer above a ground shield for output matching. The millimeter-wave transformer has a high coupling factor k = 0.8 and provides a very compact circuit layout. At 61.5 GHz the class-AB biased amplifier achieves a power gain of 12 dB with 8.5 dBm output power at a 1 dB compression. The saturated output power was measured up to P/sub sat/ = 14 dBm with a maximum PAE of 4.2%.

RF CMOS for microwave and mm-wave applications

RF CMOS is gaining significant momentum as the technology of choice for implementing product designs in the 1-10GHz band. With scaling pushing fT and fMAX of FETs beyond 300GHz and integration of back-end-of-line (BEOL) conducive to low-loss passives, CMOS is poised to address application needs in the X, K and V bands

Characterization of TSV-Induced Loss and Substrate Noise Coupling in Advanced Three-Dimensional CMOS SOI Technology

Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4s) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.

Design and Modeling Methodology of Vertical Interconnects for 3DI Applications

This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level models have been developed based on explicit expressions. The pronounced frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as skin and proximity effects. The models have been verified against numerical computations (full wave HFSS and quasi-static Q3D solvers). A dedicated test site has been designed for broadband characterization (from 1 MHz up to 110 GHz) of TSVs within a dense farm.