Jingbo Ye

Total ionization dose effects and single-event effects studies of a 0.25 µm Silicon-On-Sapphire CMOS technology

The total ionization dose effects and the single event effects in a 0.25 mum Silicon-On-Sapphire CMOS process are studied with a total dose of 100 krad(Si) and a fluence of 1.8times1012 proton/cm2. The results indicate that this process is radiation tolerant.

The CLEO-III ring imaging Cherenkov detector

Abstract The CLEO detector has been upgraded to include a state of the art particle identification system, based on the Ring Imaging Cherenkov detector (RICH) technology, in order to take data at the upgraded CESR electron positron collider. The expected performance as well as the preliminary results are reviewed from an engineering run during the first few months of operation of the CLEO III detector.

Optical data transmission ASICs for the high-luminosity LHC (HL-LHC) experiments

We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments.

Total ionizing dose and single event effect studies of a 0.25μm CMOS serializer ASIC

A 0.25 μm CMOS serializer ASIC, designed using radiation tolerant layout practice, was exposed to proton beam at various flux levels and accumulated fluence over 1.9times1015 protons/cm2 (100 Mrad (Si)). The ASIC survived this total ionizing dose (TID) with no degradation in function. Single event effect (SEE) cross-sections are also calculated.

The VCSEL-based array optical transmitter (ATx) development towards 120-Gbps link for collider detector: development update

A compact radiation-tolerant array optical transmitter module (ATx) is developed to provide data transmission up to 10Gbps per channel with 12 parallel channels for collider detector applications. The ATx integrates a Vertical Cavity Surface-Emitting Laser (VCSEL) array and driver circuitry for electrical to optical conversion, an edge warp substrate for the electrical interface and a micro-lens array for the optical interface. This paper reports the continuing development of the ATx custom package. A simple, high-accuracy and reliable active-alignment method for the optical coupling is introduced. The radiation-resistance of the optoelectronic components is evaluated and the inclusion of a custom-designed array driver is discussed.

Component Prototypes Towards a Low-Latency, Small-Form-Factor Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade

This paper presents several component prototypes towards a low-latency, small-form-factor optical link designed for the ATLAS Liquid Argon Calorimeter Phase-I trigger upgrade. A prototype of the custom-made dual-channel optical transmitter module, the Miniature optical Transmitter (MTx), with separate transmitter optical sub-assemblies (TOSAs) has been demonstrated at data rates up to 8 Gbps per channel. A Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC has been developed and is used in the current MTx prototypes. A serializer ASIC prototype, operating at up to 8 Gbps per channel, has been designed and tested. A low-latency, low-overhead encoder ASIC prototype has been designed and tested. The latency of the whole link, including the transmitter latency and the receiver latency but not the latency of the fiber, is estimated to be less than 57.9 ns. The size of the MTx is 45 mm ×15 mm ×6 mm.

The 120Gbps VCSEL Array Based Optical Transmitter (ATx) development for the High-Luminosity LHC (HL-LHC) experiments

The integration of a Verticle Cavity Surface-Emitting Laser (VCSEL) array and a driving Application-Specific Integrated Circuit (ASIC) in a custom optical array transmitter module (ATx) for operation in the detector front-end is constructed, assembled and tested. The ATx provides 12 parallel channels with each channel operating at 10 Gbps. The optical transmitter eye diagram passes the eye mask and the bit-error rate (BER) less than 10(-12) transmission is achieved at 10 Gbps/ch. The overall insertion loss including the radiation induced attenuation is sufficiently low to meet the proposed link budget requirement.

High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers

We develop a custom Bit Error Rate test bench based on Altera’s Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial stand alone tester. The 8B/10B protocol is implemented and its effects studied. A variable optical attenuator is inserted in the fibre loop to induce transmission degradation and to measure receiver sensitivity. We report comparable receiver sensitivity results using the FPGA based tester and commercial tester. The results of the FPGA also shows that there are more one-tozero bit flips than zero-to-one bit flips at lower error rate. In 8B/10B coded transmission, there are more word errors than bit flips, and the total error rate is less than two times that of non-coded transmission. Total error rate measured complies with simulation results, according to the protocol setup.

The Design of a High Speed Low Power Phase Locked Loop

The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25-μm Silicon-onSapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79 – 5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented.

Development of A 16:1 serializer for data transmission at 5 Gbps

Radiation tolerant, high speed and low power serializer ASIC is critical for optical link systems in particle physics experiments. Based on a commercial 0.25 μm silicon-onsapphire CMOS technology, we design a 16:1 serializer with 5 Gbps serial data rate. This ASIC has been submitted for fabrication. The post-layout simulation indicates the deterministic jitter is 54 ps (pk-pk) and random jitter is 3 ps (rms). The power consumption of the serializer is 500 mW. The design details and post layout simulation results are presented in this paper.