Bernd-Ulrich Klepser

A 10 GHz SiGe BiCMOS phase-locked-loop frequency synthesizer

A SiGe BiCMOS phase-lock-loop circuit is presented. A maximum operational frequency of 10 GHz and a current consumption of 7.6 mA, i.e. 17 mW is demonstrated. For a 9 mW low power version, a maximum frequency of 4.7 GHz is determined. This demonstrates the speed and power advantage of the SiGe BiCMOS technology for wireless communications.

A 5.7 GHz Hiperlan SiGe BiCMOS voltage-controlled oscillator and phase-locked-loop frequency synthesizer

A SiGe BiCMOS 5.5-6.4 GHz frequency synthesizer is presented. The synthesizer consists of an oscillator with a phase noise of -110 dBc/Hz at 1 MHz offset, and a 10 GHz phase-lock-loop circuit with an in-band phase noise of -79 dBc/Hz. The power consumption of the ICs was 9 mW and 17 mW, respectively.

2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS

Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2], in the feedback or reference path of a phase-locked loop (PLL) [3,4] or as direct phase modulators in outphasing transmitters (OT) [5]. While DTCs in PLLs often operate close to the reference oscillator frequency, CDR and OT DTCs are required to operate at frequencies in the GHz range. DTCs are often built using a multistage segmented architecture, employing separate coarse and fine delay tuning.

A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and fine tuning blocks, respectively. Control logic is implemented to prevent shoot-through current during the interpolation process in order to linearize the PI. The measured DTCs peak integral nonlinearity (INL) is 1.2 ps and limited by the PI. The interpolation process is analyzed in detail, describing the root cause of the nonlinearity and indicating key parameters to improve it. Furthermore, a measurement method for DTCs is presented that enables femtosecond accuracy. The DTC has been implemented in standard 28 nm CMOS technology.