Ashoke Ravi

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

A class-E power amplifier (PA) utilizes differential switches and a tuned passive output network improves power-added efficiency (PAE) and insensitivity to amplitude variations at its input. A modulator is introduced that takes outphased waveforms as its inputs and generates a pulse-width and pulse-position modulated (PWPM) signal as its output. The PWPM modulator is used in conjunction with a class-E PA to efficiently amplify constant envelope (e.g., GMSK) and non-constant envelope (e.g., QPSK, QAM, OFDM) signals with moderate peak-to-average ratios (PAR). The measured maximum output power of the PA is 28.6 dBm with a PAE of 28.5%, and the measured error vector magnitude (EVM) is 1.2% and 4.6% for GMSK and pi/4-DQPSK (PAR ap 4 dB) modulated signals, respectively.

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

A 2.4 GHz outphasing power amplifier (PA) is implemented in a 32 nm CMOS process. An inverter-based class-D PA topology is utilized to obtain low output impedance and good linearity in the outphasing system. MOS switch non-idealities, such as finite on-resistance and finite rise and fall times are analyzed for their impact on outphasing linearity and efficiency. Outphasing combining is performed via a transformer configured to achieve reduced loss at power backoff. The fabricated class-D outphasing PA delivers 25.3 dBm peak CW power with 35% total system Power Added Efficiency (includes all drivers). Average OFDM power is 19.6 dBm with efficiency 21.8% when transmitting WiFi signals with no linearization required. The PA is packaged in a flip-chip BGA package. Good linearity performance (ACPR and EVM) demonstrates the applicability of inverter-based class-D amplifiers for outphasing configurations.

A 2.4-GHz 20–40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based phase modulator delays incoming LO edges with a resolution of 1.4 ps (8 bit) required to meet WiFi requirements. A phase MUX architecture is proposed to implement switching between phases once every LO period (2.4 GHz) without generating detrimental glitches at the output. Due to its open-loop nature, the proposed phase modulator is capable of delivering wide OFDM bandwidths up to 40 MHz. The paper analyzes the impact of impairments, e.g., delay mismatch within the delay cells and outphasing mismatches, as well as associated mitigation techniques. The transmitter has been implemented in a 32-nm digital CMOS process and delivers an OFDM average power of 20 dBm with an overall system efficiency of 18.6% when transmitting 54-Mb/s 64QAM signal. The fully digital design is expected to further improve in power dissipation and chip-area with further CMOS scaling.

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS

A 5-bit flash ADC incorporates 20 mum by 20 mum inductors to improve both comparator preamplification bandwidth and regeneration speed. A switched-cascode scheme reduces comparator kickback. Offset cancellation is achieved by modifying the comparator reference voltages without degrading high-speed performance. The ADC achieves a measured SNDR of 27.5 dB for a 5 MHz input at 4 GS/s, and 23.6 dB for a 1 GHz input at 3.5 GS/s. The power consumption (including clock buffer and ladder) is 227 mW at 3.5 GS/s. The active area is 0.658 mm2

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement

A transformer-combined fully integrated outphasing class-D PA in 45 nm LP CMOS achieves 31.5 dBm peak output power at 2.4 GHz with 27% peak PAE, and supports over 86 dB of output power range. The PA employs dynamic power control (DPC) whereby sections of the PA are turned on or off dynamically according to the instantaneous signal amplitude to reduce power dissipation, especially at back-off. Dynamic on-off switching introduces transients on the power supply that can limit performance. The paper proposes and demonstrates techniques to reduce the impact of such transients. A multi-section slab inductor based transformer combiner is used to allow individual switching of unit PAs. The PA delivers 24.8 dBm average power while meeting 64-QAM WLAN requirements. PAE is 16% when using DPC, which represents a 33% efficiency enhancement compared to the DPC-disabled mode. At lower average power of 20.5 dBm, DPC enables a 140% enhancement in average efficiency, hence increasing battery life.

An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18 /spl mu/m digital CMOS process

We present a 5 GHz, voltage controlled quadrature oscillator, based on transformer coupling between the quadrature components. The oscillator is fabricated in a 0.18 /spl mu/m, low voltage digital CMOS process with a lossy substrate (/spl rho//spl sim/10mohm-cm) and thin, high resistivity metallization. Fully integrated low Q (/spl sim/4) spirals form the transformer windings in the resonators. The coupling has been optimized to obtain quadrature accuracy with minimum phase noise degradation. The VCO achieves a tuning range of /spl sim/1 GHz, and a phase noise of up to -123 dBc/Hz at a 1 MHz offset, while drawing 7.5 mA at 1.6 V. An image reject receiver built using the onwafer quadrature signals, provides 43 dB of image rejection, confirming better than 1/sup 0/ of quadrature matching.

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

In this paper, we present a 39.1-to-41.6 GHz 1.2 V 64 mW DeltaSigma fractional-N frequency synthesizer that is implemented in 90nm CMOS. To reduce power consumption, a divide-by-4 injection-locking frequency divider (ILFD) is used in the feedback loop and a digital calibration technique is implemented to overcome the ILFD locking-range limitations.

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS

Integration of radios in SoCs along with digital baseband and application processors is desirable for cost and form-factor reasons. Digital processors are typically implemented in the latest CMOS process to take advantage of the increased density and performance afforded by CMOS scaling. Integration of traditional RF circuits, however, requires accurate RF and passive models that typically lag behind digital transistor models by several quarters. This makes RF integration the limiting factor for time-to-market for the whole SoC, or results in sub-optimal multiple-chip solutions. Furthermore, traditional RF circuits do not benefit from scaling as digital circuits do, e.g. due to extensive use of inductors, the ever-lowering supply voltage, etc. This work presents a digital WiFi transmitter (TX) implemented in a 32nm digital CMOS process to address these issues. An outphasing architecture allows implementation of both amplitude and phase modulation using scaling-friendly, delay-based, switching phase modulators. The integrated PA was already shown to be possible to design with no RF models [1]; known issues of outphasing PA design (e.g. output impedance modulation, linearity, efficiency) are also addressed in [1]. The phase modulator uses an open-loop architecture to accommodate OFDM bandwidths up to 40MHz. The TX achieves state-of-the-art performance already in 32nm and is moreover expected to: (1) improve with scaling and (2) port easily over successive process nodes.

A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application

An outphasing power amplifier (PA) is designed and implemented in a 32nm digital CMOS process. The PA uses a transformer power combining configuration with reduced losses at backoff power. In the range of 2.2–2.5GHz, this PA gives 25dBm peak CW power with 40% total efficiency (includes all drivers). The class-D PA takes advantage of 32nm switching speed to achieve good linearity performance. The PA delivers 18dBm average power with 18% total efficiency while meeting 64-QAM WLAN requirements, with no need for linearization.