Bharat Krishnan

Eliminating arsenic containing residue that create killer defects in 20 nm HVM

Dry oxide removal techniques are used as pre-spacer cleans to remove sidewall oxide (without undercutting the gate oxide and maintaining the gate CD (critical dimension)) in 20 nm HVM (high volume manufacturing). This results in arsenic containing residues on the wafer surface. Dry etch, although effective in accomplishing most of the desired process objectives, is not effective in removing arsenic, implanted into the oxide during the junction formation. As a result, arsenic residues are left on the wafer surface after the pre-spacer clean which then get coated by spacer nitride. Nitride-coated arsenic residues are difficult to remove and new cleans were developed to completely remove arsenic residue from the wafer surface at the pre-Spacer clean step. Defectivity reduction and electrical data are presented to show the effectiveness of these new cleans and the resultant yield increase, respectively.

Effect of Si precursors on micro-loading, morphology and throughput of selective epitaxial growth of si and Si 1−x Ge x

In this paper, we report the effect of two Si precursors, SiH₄ and SiCl₂H₂ on the micro-loading, morphology and throughput for selective epitaxial growth of Si and Si_1-xGe_x (0<;x<;1) on recessed or elevated source/drain junctions. We find that the pattern dependency (micro-loading), growth direction (morphology) and growth rate of selective epitaxial film of Si or Si_1-xGe_x can be engineered by carefully adjusting the ratio of partial pressures of SiH₄ and SiCl₂H₂.

Effect of defectivity reduction in Spacer and Junction modules on RMG defectivity

Defect elimination from the Spacers and Junctions modules has been shown to increase yield in 20 nm HVM (high volume manufacturing). However, other defects such as surface particles and lifted pattern were also found in these modules. These defects formed voids downstream and later were filled with metals in the RMG (replacement metal gate) process. Therefore, these defects also need to be eliminated in order to meet entitlement yield. These defects were traced through the line from their origination in the Spacer and Junction modules into RMG and MOL (middle of line) modules. Surface particles and lifted pattern were eliminated by developing a new photoresist stripping (PRS) process. The effectiveness of the new PRS process was verified by defect elimination in the Spacer and Junctions and in the downstream RMG module. Defectivity reduction and electrical data will be presented to show the effectiveness of this new PRS process.

Experimental investigation and manufacturing solution of the rapid thermal process induced overlay residue

Experimental investigation for rapid thermal process (RTP) induced overlay residue was conducted. Silicon wafer substrate played a critical part in the RTP induced overlay residue. Substrates with epitaxial layers showed better overlay performance. High device densities tended to show worse overlay residue performance with same RTP process condition. Shallow trench isolation (STI) aspect ratio was one of the major factors that led to severe RTP induced overlay residue. A very minor temperature change at wafer edge during STI liner oxidation could cause significant overlay residue for products with high STI aspect ratio. The experiments revealed that the RTP process chamber temperature controller alone did not exhibit a significant impact to the overlay performance. Better thickness or sheet resistance uniformity did not ensure a better overlay residue performance. In fact, it could be necessary to sacrifice a certain level of thickness or sheet resistance (Rs) uniformity to ensure the following mask process overlay residue within specification. One of the manufacturing solutions was to control the temperature delta of probe seven minus probe six. Another solution was to use a reusable simple short loop wafer to verify the chamber was healthy after major maintenance or critical parts change.