Bhusan Gupta

Panel: Reconfigurable SoC- What will it look like

The argument against ASIC SoCs is that they havealways taken too long and cost too much to design. Asnew process technologies come on line, the issue ofinflexible, unyielding designs fixed in silicon becomes aserious concern. Without the flexibility of reconfigurablelogic, will standard cell ASICs disappear and go the wayof gate arrays? Will ASIC manufacturers lose their edgein providing intellectual value and become merepurveyors of square die area?The argument in favor of FPGAs is that they havealways provided great design flexibility because theywere configurable. The argument against FPGAs is thatcompared to ASICs they have always been larger, slowerand more expensive. Will FPGAs ever become efficientenough to replace ASICs in volume productionapplications? ASSPs can be designed with partialreconfigurability. Will they become the norm? Or, willnew reconfigurable logic cores change the SoC gamecompletely?The answers to these questions will clearly impactsystem designers throughout the world and shape thefuture of the electronics industry. A panel of key industryexecutives each coming from a different area of themarket with unique views will debate these highlycontroversial topics.

Different Approaches to Add Reconfigurability in a SoC Architecture

Summary form only given. Dynamically reprogrammable hardware has been advocated in the academic research community as the next hot area in system design for some time now. The lack of integrated systems in the marketplace that incorporate dynamic reprogramming stands at contrast to the enthusiasm of the research community for the topic. We would like to offer as a middle ground several examples of dynamic reprogramming in working silicon that might help to illuminate the path towards the future of SoCs. In our research at STMicroelectronics, we have built two independent SoCs that utilize embedded FPGAs to provide the dynamic reprogramming capability. The benefit of the embedded FPGA has been demonstrated to range from application acceleration to augmenting functionality and providing silicon area reuse. The first system to be described is intended for image processing and biometric recognition. The second system is aimed at wireless LAN baseband processing.