Bhyrav Mutnury

Finite-difference modeling of noise coupling between power/ground planes in multilayered packages and boards

Multilayered packages and boards, such as high performance server boards, contain thousands of signal lines, which have to be routed on and through several layers with power/ground planes in between. There can be noise coupling not only in the transversal direction through the power/ground planes in such a structure, but also vertically from one plane pair to another through the apertures and via holes. In addition, the continuous increase in power demand along with reduced Vdd values results in significant current requirement for the future chips. Hence, the parasitic effects of the power distribution system become increasingly more critical regarding the signal integrity and electromagnetic interference properties of cost-effective high-performance designs. We present a multilayer finite-difference method (M-FDM), which is capable of characterizing such noise coupling mechanisms. This method allows considering realistic structures, which would be prohibitive to simulate using full-wave simulators

Macromodeling of nonlinear digital I/O drivers

In this paper, a modeling technique using spline functions with finite time difference approximation is discussed for modeling moderately nonlinear digital input/output (I/O) drivers. This method takes into account both the static and the dynamic memory characteristics of the driver during modeling. Spline function with finite time difference approximation includes the previous time instances of the driver output voltage/current to capture the output dynamic characteristics of digital drivers accurately. In this paper, the speed and the accuracy of the proposed method is analyzed and compared with the radial basis function (RBF) modeling technique, for modeling different test cases. For power supply noise analysis, the proposed method has been extended to multiple ports by taking the previous time instances of the power supply voltage/current into account. The method discussed can be used to capture sensitive effects like simultaneous switching noise (SSN) and cross talk accurately when multiple drivers are switching simultaneously. A comparison study between the presented method and the transistor level driver models indicate a computational speed-up in the range of 10-40 with an error of less than 5%. For highly nonlinear drivers, a method based on recurrent artificial neural networks (RNN) is discussed.

Layout-level synthesis of RF inductors and filters in LCP substrates for Wi-Fi applications

A fast and accurate layout-level synthesis and optimization technique for embedded passive RF components and circuits such as inductors and bandpass filters have been presented. The filters are composed of embedded inductors and capacitors in a multilayer liquid crystalline polymer substrate. The proposed approach is based on a combination of segmented lumped-circuit modeling, nonlinear mapping using polynomial functions, artificial neural network-based methods, and circuit-level optimization. Synthesis and optimization results of inductors for spiral/loop designs based on microstrip and stripline configuration are within 5% of data obtained from electromagnetic (EM) simulations. For RF circuits, the methodology has been verified through synthesis of 2.4- and 5.5-GHz bandpass filters with and without transmission zeros. Scalability has been shown over a range of 2-3 and 4-6 GHz, respectively, with bandwidth variation of 0.5%-3% of center frequency. The synthesized models are within 3%-5% of EM simulation data.

Macro-modeling of non-linear I/O drivers using spline functions and finite time difference approximation

In this paper a modeling methodology using spline functions with finite time difference is proposed for modeling digital I/O drivers. Digital driver circuits can be accurately modeled using their static characteristics for normal excitations, but for faster excitations static characteristic models tend to lose their accuracy as the dynamic characteristics start to dominate the static characteristics. Spline function with finite time difference modeling includes previous time instances to capture dynamic characteristics for accurate modeling of digital drivers. In this paper the speed and accuracy of the proposed method is analyzed and compared with Radial Basis Function (RBF) modeling for different test cases.

Modeling of power supply noise using efficient macro-model of non-linear driver

In this paper, power supply noise is modeled accurately using efficient macro-models of nonlinear digital drivers. A spline function with finite time difference approximation modeling technique takes into account both the static and the dynamic memory characteristics of the driver during modeling. For power supply noise analysis, the above method has been extended to multiple ports by taking the previous time instances of the power supply voltage/current into account. The method discussed can be used to capture sensitive effects like simultaneous switching noise (SSN) and crosstalk accurately, when multiple drivers are switching simultaneously. A comparison study between the presented method and the transistor level driver models indicate a computational speed-up in the range of 10-40 with an error of less than 5%. For highly nonlinear drivers, a method based on artificial neural networks (ANN) is briefly discussed to capture SSN.

Statistical modeling of a multi-drop source synchronous bus

Using the source synchronous switching technique, high data rates can be achieved on the system board. When designing a source synchronous board, the goal is to minimize the variations in the differential delay between the data and strobe lines. This delay is often affected by jitter caused by power supply noise, cross talk, reflections and other signal integrity violations. This paper investigates the inter-relationships between electrical parameters in a printed circuit board to the physical manufacturing parameters for a source synchronous bus. Using sensitivity functions and statistical distributions of the physical parameters, the variations of the electrical parameters are computed. The correlation matrix between the electrical parameters can be used to understand the sensitivity of various electrical and physical parameters for the performance of the bus. This information can be used for redesigning boards by accounting for manufacturing variations.

Macro-modeling of transistor level receiver circuits

A modeling methodology for macro-modeling transistor level receiver circuits has been proposed. A few receiver modeling techniques have been proposed in the past, but these modeling techniques only address the loading effect of the receiver circuits i.e., the input characteristics of the receivers. In this work, the proposed modeling approach addresses both the loading effect of the receiver as well as the output characteristics of the receiver. The proposed modeling technique is simple, accurate and has huge computational speed-up over transistor level receiver circuits. A recurrent neural network (RNN) model is used to model the loading effect of the receiver. The output characteristics of the receiver is modeled using a combination of receiver static characteristics and a delay element that takes into account the timing delay of the receiver. The accuracy of the modeling approach has been tested on a few test cases and results show good accuracy.

Macromodeling of nonlinear transistor-level receiver circuits

In this paper, a modeling methodology for macromodeling transistor-level receiver circuits has been presented. A few receiver modeling techniques have been proposed in the past, but these modeling techniques only address the loading effect of the receiver circuits, i.e., the input characteristics of the receivers. In this paper, a modeling methodology that addresses both the loading effect as well as the output characteristics of the receiver has been proposed. This modeling technique is simple, accurate, and has huge computational speed-up over transistor-level receiver circuits. To model the input characteristics of the receiver, spline function with finite time difference (SFWFTD) and recurrent neural network (RNN) modeling methods have been used. The output characteristics of the receiver are modeled using a combination of receiver static characteristics and a delay element that takes into account the timing delay of the receiver. The accuracy of the modeling approach has been tested on some test cases and results show good accuracy and substantial speed-up compare to transistor-level receiver circuits. The proposed modeling technique has been extended to multiple ports to estimate sensitive effects like simultaneous switching noise (SSN) when multiple receivers are switching.

Macro-modeling of non-linear pre-emphasis differential driver circuits

Differential signaling has become important in high speed digital and mixed signal systems because of its numerous advantages over single-ended signaling. Differential signaling reduces effects like simultaneous switching noise (SSN), electro magnetic interference (EMI) and crosstalk coupling. Signal integrity (SI) and timing analysis using differential drivers is computationally exhaustive due to increased complexity in design that includes features such as pre-compensation and slew rate control. Therefore, accurate macro-modeling of differential driver circuits for a quality design is a huge challenge. In this paper, a modeling technique based on recurrent neural network (RNN) is proposed to model differential driver circuits with and without pre-emphasis. Good accuracy is obtained in the test cases shown for the proposed modeling methodology at minimum computational cost.

Scalable driver I/O macromodels for statistical analysis

In this paper, scalable driver I/O macromodels have been proposed for efficient signal integrity and timing analysis of todays high-speed systems. Variations in semiconductor process, temperature, and power supply voltage affect the output voltage and current in driver circuits. The effect of these variations on driver and receiver circuits has been captured using Lagranges interpolation technique. In this paper, scalable macromodeling approach has been applied to differential driver circuits and single-ended driver and receiver circuits. Scalable driver and receiver circuits consume less CPU memory and simulation time compared to transistor-level driver and receiver circuits. The accuracy of scalable macromodels has been tested on various test cases for differential driver and single-ended driver-receiver circuits and results yielded good accuracy.