Biagio Bisanti

A fully integrated zero-IF transceiver for GSM-GPRS quad band application

A GPRS GSM850/GSM/DCS/PCS fully integrated transceiver occupies 14mm/sup 2/ in 0.35/spl mu/m SiGe technology. A direct conversion receiver, transmitter, synthesizer, VCO, voltage regulators and loop filters are fully integrated. The chip meets the GPRS specifications including settling time of 105/spl mu/s in RX mode, NF of 3dB for GSM, TX phase error of 2/spl deg/ RMS, and PLL phase noise of -84dBc/Hz at a 1kHz offset at 3.6GHz.

Direct Sigma Delta GMSK modulator modeling and design for 2.5 G TX applications

This paper proposes a new Simulink modeling technique for an SD kind of modulator. In fact the system analysis for this kind of design cannot use the standard tools used to design classical analog transmitters. In this solution the digital section is predominant on the analog one, but the analog behavior of the TX path has to be evaluated as a function of different analog and digital parameters. In particular the model has been used to study the impact of the analog transfer function of the PLL on a GMSK modulation. The model allows us to find the right pre emphasis filter and implementation. Different kinds of Sigma Delta have been analyzed and a 1-1-1 Mash structure has been selected. This model has been used to study and define a direct Sigma Delta modulator for 2.5 G applications and the measurements on the implemented TX section show very good agreement with the model results.

Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction

3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and other design techniques have been used. The maximum composite spurious (due to PLLs coupling, Xtal spurious and fractional spurs) is -35 dBc (in +/-15 MHz range). Each PLL has a frequency range from 2.2 GHz to 4.4 GHz with a worst-case (over process and temperature) integrated rms of 1.2 deg at 3.8 GHz. The frequency step (31.25 KHz) is obtained with a 10 bit SD clocked at 32 MHz. The single PLL draw 35 mA from 3.8 Volt supply (regulated internally to 2.8 or 3.4 Volt) for 3.2 mm2.