Eric Duvivier

A fully integrated zero-IF transceiver for GSM-GPRS quad band application

A GPRS GSM850/GSM/DCS/PCS fully integrated transceiver occupies 14mm/sup 2/ in 0.35/spl mu/m SiGe technology. A direct conversion receiver, transmitter, synthesizer, VCO, voltage regulators and loop filters are fully integrated. The chip meets the GPRS specifications including settling time of 105/spl mu/s in RX mode, NF of 3dB for GSM, TX phase error of 2/spl deg/ RMS, and PLL phase noise of -84dBc/Hz at a 1kHz offset at 3.6GHz.

Low-IF 90nm CMOS receiver for 2.5G application

In this paper, a pure digital CMOS (90nm) dual-band GSM low IF (100kHz) receiver section is presented. The incoming RF signal is first amplified using two differential LNAs (one for GSM and the other for DCS) and then down converted by two passive mixers to produce the low frequency I and Q signals. The 90 degrees phase shifted local oscillator signals are implemented on chip using two dividers by 4 and by 2 (working at 3.6GHz). The low IF strip will amplify and filter the I and Q signals. It has been built with digitally programmable gain stages including also a Butterworth 2nd order polyphase active filter. The receiver has been designed to be compatible with a standard 10-bits ADC. The RX chain shows state-of-the-art NF performances (<2dB in GSM and <3dB in DCS) with an overall current consumption of 29mA at 1.4V supply (9mA for the LNA, 17mA for the IF strip and 3mA for the divider by 2). The die area is 1.4mm/spl times/2.8mm.

Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction

3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and other design techniques have been used. The maximum composite spurious (due to PLLs coupling, Xtal spurious and fractional spurs) is -35 dBc (in +/-15 MHz range). Each PLL has a frequency range from 2.2 GHz to 4.4 GHz with a worst-case (over process and temperature) integrated rms of 1.2 deg at 3.8 GHz. The frequency step (31.25 KHz) is obtained with a 10 bit SD clocked at 32 MHz. The single PLL draw 35 mA from 3.8 Volt supply (regulated internally to 2.8 or 3.4 Volt) for 3.2 mm2.

Gain/bandwidth programmable PA control loop for GMS/GPRS quad-band applications

The analog power amplifier (PA) control loop of a fully-integrated GSM/GPRS quad band transceiver by Duvivier et al. (2003) is presented. The control loop is based on a fully-integrated PA controller which meets all GSM/GPRS specifications. Both the gain and the bandwidth of the PA control loop are programmable as well as the stand-by voltage delivered to the PA. These features, together with a high driving capability (8.4 mA @ 2.5 V), make this solution capable to interface vast combinations of PAs, couplers and detectors. The proposed PA controller has been integrated in a BiCMOS SiGe 0.35 /spl mu/m process and measures 0.33 mm/sub 2/. The current consumption is 2.8 mA without load and 7.2 mA in the application (using Hitachi PF08109B PA) from a single 2.8 V power supply.