Bill C. Wong

A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter

This single-ended 12b 20 MSample/s pipeline ADC has good performance for Nyquist frequency inputs. Architecture and calibration algorithms minimize digital correction circuitry and noise crosstalk. The single-ended performance is achieved with a novel input common-mode feedback technique in the S/H stage. The total power dissipation is only 250 mW from a single 5 V supply.

A pipeline A/D converter architecture with low DNL

A pipeline analog-to-digital converter architecture can reduce the differential nonlinearity (DNL) with a swapping technique without involving special calibration techniques. An implementation of the overrange stages in the analog pipeline suitable for high-speed applications is proposed. A 14-bit 5-MSample/s converter has been fabricated in a double-poly 0.5-/spl mu/m CMOS process. The 3.3/spl times/3.3 mm/sup 2/ chip dissipates 320 mW from a single 5 V supply and achieves a signal-to-noise ratio of 79 dB, a dynamic range of 82 dB, and a DNL below 0.4 LSB.

A 12b 50MSPS 34mW pipelined ADC

A 12 bit 50 MSPS pipelined ADC is fabricated in 0.18 mum CMOS process. Internal reference buffers without off-chip capacitors are implemented under 1.8 V power supply voltage for 2 Vp-p input signal swing. Opamp sharing and removal of explicit S/H stage are utilized for low power dissipation. Occupying 1.81times0.76 mm2, ADC achieves SNR of 70.4 dBFS, SFDR of 86 dBFS and ENOB of 11.3 b at Fin of 10 MHz. It consumes 34 mW with FOM of 0.27 pJ/Step.