Laurence D. Lewicki

A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter

This single-ended 12b 20 MSample/s pipeline ADC has good performance for Nyquist frequency inputs. Architecture and calibration algorithms minimize digital correction circuitry and noise crosstalk. The single-ended performance is achieved with a novel input common-mode feedback technique in the S/H stage. The total power dissipation is only 250 mW from a single 5 V supply.

Bias optimization for switched capacitor amplifiers

Bias optimization is one of the most important design issues in many low power applications. Several biasing schemes for switched capacitor applications are analyzed in this paper from the settling time point of view. A bias circuit is described that provides the best tradeoff between the slew-rate and the unity gain bandwidth of a single dominant-pole opamp over process and temperature variations. Theoretical analysis and simulations confirm a quasi-constant settling time with minimal process dependence.