Ion E. Opris

Plasma-etched neural probes

Abstract A new method is presented for microfabricating silicon-based neural probes that are designed for neurobiology research. Such probes provide unique capabilities to record high-resolution signals simultaneously from multiple, precisely defined locations within neural tissue. The fabrication process utilizes a plasma etch to define the probe outline, resulting in sharp tips and compatibility with standard CMOS processes. A low-noise amplifier array has been fabricated through the MOSIS service to complete a system that has been used in multiple successful physiological experiments.

A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter

This single-ended 12b 20 MSample/s pipeline ADC has good performance for Nyquist frequency inputs. Architecture and calibration algorithms minimize digital correction circuitry and noise crosstalk. The single-ended performance is achieved with a novel input common-mode feedback technique in the S/H stage. The total power dissipation is only 250 mW from a single 5 V supply.

A rail-to-rail ping-pong op-amp

A rail-to-rail ping-pong op-amp achieves offset cancellation and 1/f noise reduction without folding of the input spectrum. The clocking scheme minimizes the clock feedthrough and the residual offset due to charge injection. With a clock frequency of 100 kHz, the residual offset is less than 100 /spl mu/V, and the input referred noise is about 225 nV/Hz/sup 1/2/. The rail-to-rail distortion at 1 kHz is lower than -71 dB. The total silicon area is 610/spl times/420 /spl mu/m/sup 2/, and the circuit dissipates 1.5 mW from a single 5 V supply.

Rail-to-rail multiple-input min/max circuit

The author presents a multiple-input min/max circuit technique that reduces the errors associated with previous analog implementations by combining a common-source voltage-mode configuration with a current-mode winner takes all circuit. The overall architecture exhibits linear complexity with the number of inputs. Both minimum and maximum two-input prototypes have been designed and built in a 2-/spl mu/m CMOS process. The active area for each circuit is 650/spl times/100 /spl mu/m/sup 2/, and the total power dissipation is 0.8 mW from a single 5-V supply. Experimental results confirm rail-to-rail operation and sharp transition regions.

Series resistance compensation in translinear circuits

The base resistance is often the primary limitation factor for the accuracy in translinear circuits. A general compensation technique for the extrinsic base resistance and the emitter series resistance is presented in this paper. The applications discussed include proportional-to-absolute-temperature (PTAT) temperature sensors and bandgap references.

Force-balanced accelerometer with mG resolution, fabricated using Silicon Fusion Bonding and Deep Reactive Ion Etching

A single crystal silicon accelerometer with mG resolution (1 G=9.81 m/s/sup 2/) has been fabricated using Silicon Fusion Bonding (SFB) and Deep Reactive Ion Etching (DRIE). This allows thick devices (up to several hundred /spl mu/m) to be defined with high aspect ratios (up to 25), resulting in high sensitivity and low cross-axis sensitivity. Prototypes use a hybrid approach, with a 1.0/spl times/1.5 mm/sup 2/ mechanical element and a capacitive sensor interface providing closed-loop force-balancing to minimize non-linearity. The bandwidth is 1 kHz and the sensitivity is 700 mV/G. The dynamic range is 44 dB, corresponding to a resolution of 35 mG for a 5 G (full scale) device and 7 mG for a 1 G device. The resolution is currently limited by 1/f noise in the electronic interface, but will be reduced with an improved design of the capacitive sensing interface (currently in fabrication), thus resulting in sub-mG resolution.

Analog rank extractors

This paper focuses on continuous-time analog rank extractors, with an emphasis on MOS circuits. Sources of errors in previous analog implementations are analyzed, and an improved multiple-input min/max circuit configuration is proposed. A generalized analog rank extractor is discussed as well as its limitations on the number of inputs and rank. In a sorting network approach, the presorting and path combination techniques are used to reduce the rank selector implementation.

A high-speed median circuit

A high-speed analog median circuit is presented using a two-stage architecture to minimize the errors around the transition corners. Prototypes have been designed and built using the Orbit 2-/spl mu/m CMOS process. The design has been optimized for low crossover distortion and fast transient recovery in less than 200 ns. The active area is 0.2 mm/sup 2/, and the circuit dissipates 7 mW from a single 5 V supply while being able to drive an external 30 pF capacitor.

Planar electrode array systems for neural recording and impedance measurements

Systems designed to significantly reduce equipment cost and size for neurophysiological studies and hybrid biosensor applications were developed. Custom integrated circuits, each providing 18 channels of amplification and filtering were designed, fabricated and tested. Planar arrays of iridium microelectrodes were fabricated and packaged in a standard 40 pin dual-in-line package for cultured cell and neural slice preparation studies. An impedance imaging system was developed to monitor the impedance of the cell/electrode interface across the array, thereby expanding the possible biosensor applications to non-electrically active cell types. Thermal regulation was achieved via a Peltier effect thermoelectric device allowing temperature control both above and below ambient temperature. While designed to work together the system components presented may be easily applied to existing systems for enhancement of capabilities while reducing size and cost.

A Videobandwidth Analog Median Circuit

An analog median circuit has been designed and built in a 2pm CMOS process. The active area is 0.18mm2, and the circuit dissipates 1 ImW from a single 5V supply. The design trade-off between speed and accuracy allows for about lOmV of “corner” errors, while the circuit settles in less than loons, making it suitable for video applications.