Bin B. Jie

Effects of energy distribution of interface traps on recombination dc current-voltage line shape

The effects of energy distributions of Si∕SiO2 interface traps in the energy gap of oxidized silicon on the current versus voltage line shape of the electron-hole recombination current are analyzed using the steady-state Shockley-Read-Hall kinetics. Slater’s [Insulators, Semiconductors and Metals; Quantum Theory of Molecules and Solids (McGraw-Hill, New York, 1967)] localized bulk perturbation theory applied by us to the interface anticipates U-shaped energy distributions of the density of neutral electron and hole interface traps from random variations of the Si:Si and Si:O bond angles and lengths. Conservation in dissipative transition energy anticipates the rate of electron capture into neutral electron trap to be faster for electron trap energy levels nearer the conduction band edge, and similarly, the rate of hole capture into neutral hole trap to be faster for hole trap energy levels nearer the valence band edge. Line shape broadening is analyzed for discrete and U-shaped energy distributions of int...

Physics-based exact analytical drain current equation and optimized compact model for long channel MOS transistors

An exact analytical formula of DC drain current versus gate and drain voltages is derived for MOS transistors with constant channel-impurity-concentration based on device physics. From this exact analytical formula, a compact model for long-channel MOS transistors is derived. The compact model is optimized over wide ranges of transistor properties by least-square-fit to numerical I-V data from the exact analytical formula. The optimized compact model has only one parameter to least-square-fit experimental data. The exact analytical formula and the compact model are verified numerically by I-V values calculated from the exact Pao-Sah double-integral formula.

Generation-Recombination-Trapping at Interface Traps In Compact MOS Transistor Modeling

Operation lifetime of logic MOS transistors, endurance of memory MOS transistors, trapping noise in analog and RF MOS transistors, and standby power dissipation in all of these transistors, have their common origin in electron-hole GRT (generation-recombination-trapping) at SiO 2/Si interface traps. Inclusion of GRT in MOS transistor model can be made using the surface-potential approach adopted by the next (second) generation compact model. This paper describes the theoretical analysis of the GRT currents in the long-wide-channel MOS transistor model to serve as the baseline for compact modeling

Evaluation of surface-potential-based bulk-charge compact MOS transistor model

The existing surface-potential-based compact metal-oxide-semiconductor transistor models are based on the 1978 Brews delta-function charge-sheet approximation, which was derived empirically from the 1966 Pao-Sah drift-diffusion double integral formula. This paper provides a device physics-based derivation of a surface-potential-based compact model by analytical approximation of the double and single bulk-charge integrals of the four one-dimensional components of the six-component 1996 Sah two-dimensional formula. In this compact model development, the mobile carrier-space-charge-limited parabolic-drift and linear-diffusion current components are analytically represented by the surface potential without approximation, while the immobile-impurity bulk-space-charge-limited double-integral drift-current and single-integral diffusion-current components are evaluated analytically using three possible surface-potential compact model approximations. This paper calculates the accuracy of these approximate analytical bulk-charge-limited drift and diffusion current components in both the inversion and subthreshold ranges and discusses factors that affect the accuracy in the subthreshold range and near flatband.

Tunnel DCIV diagnosis of ultrathin gate oxide metal-oxide-silicon transistors

The dc tunnel current–voltage method (tunnel DCIV) is demonstrated in this paper as a potential diagnostic monitor for process parameter variations of future generations of metal-oxide-silicon transistors. An example is given of p-channel metal-oxide-silicon transistors fabricated by 100 nm technology with 12.5 A gate oxide. Tunnel current pathways in the gate oxide are described. Two figures of merit from the tunnelling current are suggested as a possible in-line monitor to evaluate process parameters in the basewell region and in the gate-overlapped drain and source extension regions. A zeroth-order one-dimension model is given to demonstrate the sensitivity of these two figures of merit.

Generation-recombination-trapping at interface traps in short-channel MOS transistors

When the MOS transistor channel shortens, terminal currents from thermal generation-recombination-trapping (GRT) of electrons and holes at SiO2/Si interface traps in the drain and source p/n junction space-charge regions and their extension regions are increasingly dominant over the shortened base-channel region. Analytic solutions of GRT currents from interface traps in the two-dimensional drain and source p/n junction space-charge regions are obtained for the very thin and very thick gate-oxide limits. As anticipated from device physics, experimental results from increasingly shorter channels (100 mum to 0.13 mum) nMOS and pMOS transistors favor the very thin oxide model for the short channel transistors

Theoretical accuracy of using Boltzmann and ionized impurity approximations in the analyses of recombination current at interface traps in metal-oxide-silicon structures

In order to provide high computation speed, the Boltzmann distribution and fully ionized impurity (BI) approximations have been used to analyze experimental recombination current data to extract interface properties of metal-oxide-semiconductor (MOS) structures. The accuracy of the BI approximation is theoretically estimated in this paper by computing its deviation from the exact Fermi distribution and de-ionizable-impurity theory. Five device and material parameters of the MOS transistor structures are varied: substrate dopant-impurity concentration, gate oxide thickness, forward source and drain junction bias, interface-trap energy level, and transistor temperature. The results show that the BI approximation gives less than 5% deviation over the practical ranges of the five parameters.

Tunnel DCIV extraction of dopant-impurity concentration, oxide thickness, and length in the channel and extension regions of ultrathin gate-oxide MOS transistors

A methodology is described for extracting, between the source and drain, the spatial variations of surface dopant-impurity concentration and oxide thickness in the channel, drain/extension and source/extension regions using experimental tunnel direct current current-voltage data of the drain, source, and basewell terminal currents versus the gate/base voltage. An example is given using an pMOS transistor with W/L=10 /spl mu/m/0.3 /spl mu/m fabricated by a factory 100-nm technology. Zeroth (constant values) and first-order (linear variation with position) representation formulas are used for the impurity concentration and oxide thickness to fit the experimental data, which also give the electrical lengths of the three regions.

Implementin spatial variation of impurity concentration in MOS transistor modeling

Analytical solution, numerical algorithms and computed curves of D. C. current-voltage characteristics are reported for MOS transistors with spatially varying impurity concentration profile in the basewell-channel region. The second generation industrial-consensus surface-potential approach is used. A family of analytical impurity concentration profiles is studied, including the exponential and Gaussian U-shaped, M-shaped, and L-shaped profiles. The current-voltage characteristics, especially in the subthreshold range, are influenced by the remote electric potential boundary conditions, including the basewell-body contact location, geometry and barrier type, and voltage

TDCIV extraction of dopant-impurity concentration and oxide thickness in ultrathin gate oxide MOS transistors

A methodology is demonstrated for lateral position profiling of surface dopant-impurity concentration in the channel region and two extension regions using experimental tunnel direct-current current-voltage (TDCIV) curves on a pMOS transistor with W/L = 10/spl mu/m/0.3/spl mu/m fabricated by a factory 100nm technology. The methodology employs a zeroth-order and a first-order TDCIV model. Based on the zeroth-order model, constant oxide thickness, constant surface substrate-dopant-impurity concentration, and region length in each region were extracted. Then, using lateral dopant-impurity profile formulae in the first-order model to fit the TDCIV drain, source and basewell current data, the spatial variations of surface dopant-impurity concentration in the three regions are obtained.