Chih-Tang Sah

Direct-current measurements of oxide and interface traps on oxidized silicon

A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density. The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping. >

Models and experiments on degradation of oxidized silicon

Abstract The concepts of electronic and protonic traps are introduced to delineate and classify the fundamental mechanisms of charging, generation, annealing and hydrogenation of electronic or electron and hole traps located in the interfacial (gate-conductor/oxide, oxide/nitride and oxide/silicon), insulator (oxide, nitride and oxynitride) and semiconductor surface layers of silicon MOS transistors and integrated circuits. Two matrix tables, one without tunneling (3 × 3) and one with tunneling (3 × 4) are used to classify the trap charging and electronic injection mechanisms according to the initial and final (band or bound) states of the electronic transition and the energy exchange mechanisms (thermal, optical and Auger-impact). The importance of tunneling to and from traps (TTT) as an oxide charge build-up mechanism is discussed. A theoretical tunneling rate to traps is given showing that traps shallower than about 2 eV from the oxide conduction band edge or 3 eV from the oxide valence band edge cannot be charged by the TTT transitions alone. Experimental examples illustrating the use of these mechanism tables as well as the importance of breaking hydrogen and strained intrinsic bonds by hot electron impact and by thermal hole capture are discussed, including: (i) annealing of the oxide/Si interface traps via hydrogenation during 380C chip bonding and during Fowler-Nordheim tunneling electron injection (FN-TEI) and avalanche electron injection (AEI) stresses, (ii) interface trap generation and positive oxide charge build-up during electron injection via FN-TEI or AEI, and (iii) electrical deactivation of boron and other group-III acceptors (Al, Ga, In) in the silicon surface layer during FNTEI or AEI stresses. Examples at three d.c. bias conditions to delineate the dominant degradation mechanisms in silicon MOS transistors are given showing that trap charging via tunneling (FNTEI, FNTHI and TTT) dominates below about 3.3 V in both n -MOS and p -MOS but trap generation via bond breaking by thermal hole capture may also occur in low voltage p -MOS. Higher than about 10 V, tunneling (FNTEI, FNTHI and TTT) and avalanche injection (AEI and AHI) as well as hydrogen and intrinsic bond-breaking may all be important degradation mechanisms.

Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors

Carrier tunneling through ultrathin (1–3 nm) SiO2 layers in MOS (metal–oxide–silicon) structures is investigated using the Bardeen–Harrison transition probability method. Quantum mechanical wave function matching at the two abrupt potential boundaries of a trapezoidal Si/SiO2/Si barrier gives an electric-field dependent preexponential factor in the Wentzel–Kramers–Brillouin tunneling probability, which significantly affects the current–voltage characteristic at low fields. An analytical theory is employed to predict the relative importance of three elastic tunneling pathways (electrons, valence electrons, and holes) and two geometrical tunneling locations (channel region and source or drain overlap regions) in MOS transistors (MOSTs), showing (1) hole tunneling dominant in p+gate pMOST (p-channel MOST) at low gate voltages, and (2) overlap regions dominant prior to base-region inversion in both p+gate pMOST and n+gate nMOST (n-channel MOST). The analytic theory is used to analyze the experimental tunnelin...

Degradation of bipolar transistor current gain by hot holes during reverse emitter-base bias stress

Experimental evidences are given which demonstrate that degradation of the common-emitter forward current gain h/sub FE/ of submicron silicon npn bipolar transistors at low reverse emitter-base junction applied voltage is caused by primary hot holes of the n/sup +//p emitter tunneling current rather than secondary hot electrons generated by the hot holes or thermally-generated hot electrons. Experiments also showed similar kinetic energy dependence of the generation rate of oxide/silicon interface traps by primary hot electrons and primary hot holes. Significant h/sub FE/ degradation was observed at stress voltages less than 2.4 V.

Two pathways of positive oxide‐charge buildup during electron tunneling into silicon dioxide film

Two positive oxide‐charge generation pathways with low voltage or kinetic energy threshold in the Si‐gate/SiO2/Si‐substrate structure are correlated with experiments. They are initiated by Fowler–Nordheim electron tunneling through sub‐10‐nm SiO2. These tunneled electrons in the polycrystalline Si gate or crystalline Si substrate generate energetic holes by two collision mechanisms: interband impact generation and interband Auger recombination. The energetic holes are then back injected into the oxide valence band by surmounting the 4.25‐eV Si/SiO2 hole barrier and captured by oxide hole traps. The calculated electron threshold energy to generate a positive oxide charge by the impact mechanism is EC‐SiO2+2.24 eV or EC‐Si+5.37 eV compared with 2.0 eV and 4.92±0.10 eV experimental data, and by the Auger mechanism, EC‐SiO2+0.0 eV or EV‐Si+4.25 eV compared with 4.25±0.26 eV experimental data.

Monitoring interface traps by DCIV method

DCIV method is demonstrated as a production monitoring tool for process-residue interface traps. The high sensitivity of the methodology attained from forward-biasing a p-n junction allows routine detection of as few as 100 active interface traps in small area MOS transistors. Examples are given for MOSTs from five different sub-half-micron production technologies. The body recombination current shows peaks around the intrinsic surface condition whose amplitude is proportional to the number of active interface traps in the mid-channel region. The variation of the peak amplitude with the forward bias voltage follows exactly the single-energy level formula, from which the interface-trap energy level can be determined to a few tenths of a kT accuracy.

Random telegraphic signals in silicon bipolar junction transistors

Random telegraphic signals (RTS) are observed in the forward‐biased dc base current of electrically stressed silicon bipolar transistors. The RTS noise in the base current is shown to originate from random trapping of electrons at the stress‐created oxide and interface traps located over the oxide‐covered emitter‐base junction space‐charge region. The observed pulse width (∼0.1–100 s), the uniform height of the pulses (∼1% of dc base current), and their dependencies on temperature and VBE (emitter/base bias voltage), exp(qVBE/nkT) with n=2, are interpreted by the two‐step model consisting of electron tunneling between the oxide and interface traps, and the recombination of Si band electrons and holes at the interface traps.

Profiling interface traps in MOS transistors by the DC current-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistors d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 /spl mu/m n-channel Si MOS transistor with about 10/sup 11/ traps/cm/sup 2/ generated by channel hot electron stress.

Comparison of time-to-failure of GeSi and Si bipolar transistors

The effects of Ge in the epitaxial-base on the reliability of Si/Ge/sub x/Si/sub 1-x//Si heterojunction bipolar transistors were investigated. The ten-year time-to-failure under emitter-base junction reverse-bias stress was measured at the designed operation voltage by the current-acceleration method and compared to that of Si bipolar junction transistors with no Ge (x=0). The investigation shows that the Ge incorporated by the reduced pressure chemical vapor deposition epitaxial technology to give the ramp-type Ge profile has no adverse effects on the transistor reliability.

THERMAL EMISSION OF TRAPPED HOLES IN THIN SIO2 FILMS

Distributed (∼1.4 eV) and discrete (<∼0.07 eV) hole traps have been detected in thermally grown, pure, thin SiO2 films using the thermally stimulated charge technique from 77 to 594 K. The distribution of hole traps has a U‐shaped density of states with a minimum at about 0.7 eV above the SiO2 valence band edge and is attributed to the amorphous band‐edge tail states from the SiO2 valence band. The discrete hole trap is located at 1.44±0.20 eV above the SiO2 valence band edge, which was attributed to the oxygen vacancy center. The experimental energy level is consistent with that calculated by Rudra and Fowler [Phys. Rev. B 35, 8223 (1987)] and by O’Reilly and Robertson [Phys. Rev. B 27, 3780 (1993)].