Zuhui Chen

Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs

In this paper, we demonstrate analytical device models and a unique subcircuit approach to physically and accurately model the dopant-segregated Schottky (DSS) gate-all-around (GAA) Si-nanowire (SiNW) MOSFETs. The direct current characteristics of the DSS GAA SiNW MOSFETs are investigated through numerical simulations and fabricated devices. Transport mechanisms are studied and explained with numerical devices from ambipolar thermionic tunneling to unipolar drift-diffusion and a combination of both as the dopant segregation doping and thickness are varied. The convex curvature in the Ids- Vds characteristics is accurately reproduced by the subcircuit compact model, and it is shown for the first time that such a unique gds-Vds characteristic in DSS devices is only feasible to be modeled by the subcircuit approach.

Interface-trap modeling for silicon-nanowire MOSFETs

Interface traps generated during device operation or stress is directly related to transistor electrical characteristics and reliability as well as critical to device performance. In this paper, an interface-trap model is included in the unified compact model (Xsim) in order to physically and accurately characterize the interface-trap behavior in silicon-nanowire (SiNW) MOSFETs. The interface-trap model is verified by TCAD simulation data. Very good agreement is achieved and the effect of interface traps is accurately captured in the drain-source characteristics of SiNW MOSFETs. The physical interface-trap model is readily applicable for circuit and reliability modeling with SiNW transistors as building blocks.

A unified compact model for emerging DG FinFETs and GAA nanowire MOSFETs including long/short-channel and thin/thick-body effects

This paper presents the characteristics of ideal double-gate/gate-all-around (DG/GAA) MOSFETs, including the long/short-channel and thin/thick-body effects. A unified compact model (Xsim) based on the unified regional modeling (URM) approach for the generic DG/GAA MOSFET is used to demonstrate the expected behaviors, which should be included in the core model describing such emerging devices.

Neutral interface traps for Negative Bias Temperature Instability

Negative Bias Temperature Instability (NBTI) is a critical reliability issue and becoming more and more seriously in the modern CMOS technology. Many models have been proposed to account for the NBTI phenomena, but most of the models are based on the popular hydrogen reaction-diffusion (R-D) mechanisms. For the first time, in this work, a neutral interface-trap model due to the random variations of bond angles and lengths of Si··Si, Si··O and Si··N bonds is applied to explain the NBTI phenomena. The unified compact model with the neutral interface traps can very well characterize stressed device performance. The neutral interface traps with energy distribution in the silicon energy gap can very well account for the root cause of NBTI fast recovery. The model is verified by TCAD simulation and experimental measurement with excellent agreement

Unified compact modeling for Bulk/SOI/FinFET/SiNW MOSFETs

This paper describes seamless transitions among various MOS devices, ranging from bulk and partially/fully-depleted SOI to double-gate FinFETs and silicon-nanowire MOSFETs. The underlying governing equations for various structures are outlined, which provide the motivation for unifying MOS compact models with the unified regional modeling (URM) approach.

Surface recombination/generation velocity in metal-oxide-silicon field-effect transistors

Photo-device efficiency and performance are limited by the surface carrier recombination because the minority carriers are lost in the recombination process which also generates heat and increases device temperature. Based on Shockley-Read-Hall steady-state theory of recombination-generation-trapping kinetics, in the paper, the recombination DC current voltage (R-DCIV) method is extended to explore the surface minority carrier recombination/generation velocity along the surface channel region in metal-oxide-silicon (MOS) transistors. It shows that the surface recombination/generation velocity is not a system constant but can be modulated by the gate voltage in the photo-devices with an MOS structure.

Effects of Transitional Layer of Gate Insulator on Recombination DC Current–Voltage Lineshape in Metal–Oxide–Semiconductor Transistors

Industry is seeking for new materials and technologies to replace SiO2 in order to suppress leakage current, improve device performance, and keep scaling without major changes in the fabrication process. The major problem of high-k dielectric implementation is the fabrication challenge to integrate high-k materials into the manufacturing processes. In this paper, the effects of transitional layer of high-k gate insulator on the electron–hole recombination direct-current current–voltage (R-DCIV) properties are theoretically analyzed using the steady-state Shockley–Read–Hall kinetics. It shows that the gate transitional layer has negligible effect on the R-DCIV lineshape due to the small change of gate capacitance induced by the transitional layer. The transitional layer of gate insulator could offer an alternative way for industry to implement high-k dielectric since the transitional layer can alleviate the fabrication challenge in the manufacturing processes of modern very-large-scale integration (VLSI) technology.