Sanford Chu

A scaleable metal-insulator-metal capacitors process for 0.35 to 0.18 /spl mu/m analog and RFCMOS

Two different material plates used for a high density metal-insulator-metal (MIM) capacitor (1.0 fF//spl mu/m/sup 2/) top plate are studied. The two MIM capacitor process differences are compared. Their processes are very compatible with standard logic processes, and can be easily integrated into 0.35 /spl mu/m down to 0.18 /spl mu/m AlCu interconnection BEOL process. Both demonstrated good DC electrical parameter results. Their temperature, voltage coefficient and matching data fit meet the needs of most analog designers. A Q value >80 at 2.45 GHz was also achieved from the RF measurement.

Source-drain symmetry in unified regional MOSFET model

This letter investigates major sources of asymmetry in a MOSFET compact model by comparing source versus bulk reference in the drain current, effective field, and effective mobility equations. Contrary to the general belief that a regional threshold voltage (V/sub t/)-based model may pose a symmetry problem, we demonstrate that even with the simple source-extrapolated V/sub t/-based model, it can be symmetric if the drain current and the effective transverse field are derived with bulk as the reference, and the lateral-field effective mobility are properly modeled.

Tunnel DCIV diagnosis of ultrathin gate oxide metal-oxide-silicon transistors

The dc tunnel current–voltage method (tunnel DCIV) is demonstrated in this paper as a potential diagnostic monitor for process parameter variations of future generations of metal-oxide-silicon transistors. An example is given of p-channel metal-oxide-silicon transistors fabricated by 100 nm technology with 12.5 A gate oxide. Tunnel current pathways in the gate oxide are described. Two figures of merit from the tunnelling current are suggested as a possible in-line monitor to evaluate process parameters in the basewell region and in the gate-overlapped drain and source extension regions. A zeroth-order one-dimension model is given to demonstrate the sensitivity of these two figures of merit.

High Performance Device Design through Parasitic Junction Capacitance Reduction and Junction Leakage Current Suppression beyond 0.1 µm Technology

High performance 0.1 µm metal oxide semiconductor field effect transistors (MOSFETs) with 70 nm physical gate length and 1.7 nm gate oxide thickness are demonstrated. By reducing the parasitic junction capacitance and suppressing the junction leakage current (Ij,leak), high-speed/low-power transistors with a superior driving current are fabricated. Careful optimization of the channel, pocket and source/drain (S/D) doping profile results in a reduction of the N+/PW area junction capacitance (Cja) to 0.8 fF/µm2 and P+/NW Cja to 0.7 fF/µm2. In addition, area diode leakage current less than 50 nA/cm2 and perimeter diode leakage current less than 0.1 fA/µm are achieved. In this work, n-type MOS (NMOS) and p-type MOS (PMOS) drive current are 625 µA/µm and 285 µA/µm, respectively, at 1.0 V with an off-state current (Ioff) of 15 nA/µm. With the reduced parasitic capacitance and the high driving current, the unloaded ring oscillator (RO) exhibits the propagation delay time of 13 ps/stage in 1.0 V operation.

Design and Optimization of Novel High Responsivity, Wideband Silicon Photodiode

Various types of proposed photodiodes fabricated using a 0.25 µm complementary metal oxide semiconductor (CMOS) technology are presented. The effects of different design layouts on the performance are compared for a wide range of light intensity, photodiode current, dark current and diode capacitance. Frequency response of these devices are also characterized and compared for different bias conditions. A high responsivity photodiode having a 3 dB bandwidth of 9.4 GHz at a reverse bias voltage of 5 V is demonstrated. The results show that the proposed photodiodes outperform the best silicon photodiodes reported so far.

A Carbon Co-implantation Technique for Formation of Steep Halo for nFET Short Channel Effect improvement and Performance Boost

For the first time, short channel effects (SCE) of the nFET has been improved while achieving a performance boost of 7% (additive to the process induced stress technique). This was achieved by realizing a steep halo profile via strategically positioned carbon regions at the source and drain extension (SDE) regions. The tailored halo profiles also decreased the overlap (Cov) and junction capacitance (Cj). In effect, a resultant 6.5% decrease in ring oscillator (RO) delay was obtained. The carbon co- implanted device has indicated no compromise in the reliability and noise performance.

High Performance 0.1um CMOS Device with Suppressed Parasitic Junction Capacitance and Junction Leakage Current

High performance 0.1μm MOSFETs with a 70nm physical gate length and 1. 7nm gate oxide thickness are demonstrated. By reducing the parasitic junction capacitance and suppressing the junction leakage current (Ileak,j), high speed/low power transistors are fabricated with a superior driving current. Careful optimization in channel, pocket and source/drain (S/D) doping profile results in a reduction of N+/PW area junction capacitance (Cja) to 0.8fF/μm 2 and P+/NW Cja to 0.7fF/μm 2 . In addition, area diode leakage current (Ileak,a) <50nA/cm2 and periphery diode leakage current (Ileak,p) <0.1fA/μm are achieved. In this work, NMOS drive current and PMOS drive current are 840μA/μm and 380μA/μm respectively, at 1.2V with an off-state current (Ioff) 15nA/μm. With the reduced parasitic capacitance and the high driving current, the unloaded ring oscillator has 10.5ps/stage at 1.2V operation.

Yield enhancement for deep-submicron CMOS process by optimizing gate poly dimension

Gate poly dimension control is one of the most critical processing conditions to device yield, because it directly determines the transistor characteristics. For a particular deep submicron CMOS analog product, it is identified that low gate poly dimension is leading to poor yield performance. Much engineering work has been designed and carried out to study the various factors that affect gate poly feature size. These factors include lithographic masking condition, poly dry etch bias, within-wafer and wafer-to-wafer non-uniformity. It is found, that the worst case combination of all these factors could create a 0.23 /spl mu/m gate poly, which drawn width is 0.35 /spl mu/m. A focus-energy-matrix experiment was performed. The correlation between gate poly processing conditions and the device performance, as well as product yield, has been established.