Bing-Yu Hsieh

A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE

This paper presents a 3.2-to-4GHz fractional spur-free ADPLL. The ADPLL is fabricated in a 0.13 mum CMOS process and packaged in QFN76. Fractional spurs are filtered by accurate digital loop-gain calibration and digital phase-noise cancellation. The ADPLL is designed to minimize the switching noise while taking advantage of digital scaling.

Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHY

Multi-format CD/DVD SoC, integrating an RF/AFE and a 1.5 Gb/s SATA PHY, is presented. It supports a 471Mb/s 18times DVD. A partial parity mode reduces SDRAM bandwidth and a power control mode minimizes the system clock rate. The 0.18mum CMOS SoC has 10M transistors, occupies 5.4 times 5.1mm2, and consumes 772mW during a 16times DVD read

A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications

A SoC, integrating RF/AFE and 1.5 Gb/s SATA PHY, is presented. It supports 471 Mb/s bit-rate at 18timesS DVD. A partial parity mode reduces SDRAM bandwidth. A power control mode minimizes system clock rate. The SoC has 10M transistors, occupies 5.4 times 5.1 mm2 in 0.18 mm CMOS process, and consumes 772 mW during 16timesS DVD read