Jing-Hong Conan Zhan

A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications

A fully-integrated 16-element 60-GHz phased-array receiver is implemented in IBM 0.12-μm SiGe BiCMOS technology. The receiver employs RF-path phase-shifting and is designed for multi-Gb/s non-line of sight links in the 60-GHz ISM band (IEEE 802.15.3c and 802.11ad). Each RF front-end includes variable-gain LNAs and phase shifters with each front-end capable of 360° variable phase shift (11.25° phase resolution) from 57 GHz to 66 GHz with coarse/fine gain steps. A detailed analysis of the noise trade-offs in the receiver array design is presented to motivate architectural choices. The hybrid active and passive signal-combining network in the receiver uses a differential cross-coupled Gysel power combiner that reduces combiner loss and area. Each array front-end has 6.8-dB noise figure (at 22°C ) and the array has -10 dB to 58 dB programmable gain from single-input to output. Sixteen 60-GHz aperture-coupled patch-antennas and the RX IC are packaged together in multi-layer organic and LTCC packages. The packaged RX IC is capable of operating in all four IEEE 802.15.3c channels (58.32 to 64.8 GHz). Beam-forming and beam-steering measurements show good performance with 50-ns beam switching time. 5.3-Gb/s OFDM 16-QAM and 4.5 Gb/s SC 16-QAM links are demonstrated using the packaged RX ICs. Both line-of-sight links (~7.8 m spacing) and non-line-of-sight links using reflections (~9 m total path length) have been demonstrated with better than -18 dB EVM. The 16-element receiver consumes 1.8 W and occupies 37.7 mm2 of die area.

A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications

The demonstration of multi-Gb/s links in the 60GHz band has created new opportunities for wireless communications [1,2]. Due to the directional nature of millimeter-wave (mm-Wave) propagation, beam steering enables longer-range non-line-of-sight (NLOS) links at these frequencies. A phased-array architecture is attractive for an integrated 60GHz transmitter (Tx) since it can attain both beam steering and higher EIRP through spatial combining. An all-RF 16-element 40-to-45GHz Tx for satellite applications [3], a 6-element 60GHz Tx with IF-path phase-shift [4], and a bi-directional 4-element 60GHz Tx/Rx with RF phase shifters [5] have been recently demonstrated in silicon. This work presents a fully-integrated phased-array Tx which supports multi-Gb/s NLOS IEEE 802.15.3c links. In addition to beamsteering, the IC has the following major features: an on-chip power sensor at each element, 3 temperature sensors, LO leakage and I/Q phase and amplitude adjustment, front-end OP1dB programmability, and an integrated modulator for pi/2-BPSK/MSK signaling (common mode in 802.15.3c). The IC integrates 2240 NPNs, 323,000 FETs and hundreds of transmission lines and is fabricated in the IBM 8HP 0.12µm SiGe BiCMOS process (fT = 200GHz).

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 mus. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under - 75 dBc. The phase noise at 400 kHz and 3 MHz are -115.6 dBc/Hz and -134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 mu m CMOS process, and occupies an active area of 0.85 mm2 and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.

A 16-element phased-array receiver IC for 60-GHz communications in SiGe BiCMOS

A 0.12-µm SiGe phased-array Rx IC for beam-steered wireless communication in the 60-GHz band is described. It has 16 RF phase-shifting front-ends with 11° digital phase resolution and hybrid passive-active RF signal combining. It achieves 7.4–7.9 dB NF (not including 12-dB array gain) over the 4 IEEE channels. The IC has a double-conversion superheterodyne Rx core with a maximum of 72 dB of power gain in 1-dB steps, and the on-chip synthesizer achieves ≪ −90 dBc/Hz Rx phase noise at 1MHz offset. The IC draws 1.8 W at 2.7 V with a die area of 38 mm2. It has been packaged with 16 antennas in a 288-pin organic BGA and phased-array beamsteering has been demonstrated, along with 5+ Gb/s wireless links using 16-QAM OFDM.

A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE

This paper presents a 3.2-to-4GHz fractional spur-free ADPLL. The ADPLL is fabricated in a 0.13 mum CMOS process and packaged in QFN76. Fractional spurs are filtered by accurate digital loop-gain calibration and digital phase-noise cancellation. The ADPLL is designed to minimize the switching noise while taking advantage of digital scaling.

Single-element and phased-array transceiver chipsets for 60-ghz Gb/s communications

This article summarizes the development of mature and highly integrated SiGe BiCMOS ICs for gigabit-per-second communications according to the requirements of the IEEE 802.15.3c and 802.11.ad-draft standards. A single-element transceiver chipset for point-to-point communications is described with emphasis on a feature-rich yet compact 60-GHz receiver. Next, a 16-element phased-array transceiver chipset for non-line-of-sight communications is described, with emphasis on a new power-efficient phased-array transmitter. Examples of gigabit-per-second line-of-sight and non-line-of-sight link experiments are provided, and system-level implementation trade-offs are discussed.

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS

In recent years, the increasing popularity of mobile devices, such as smart- phones and tablets, is driving the demand for integrating multiple radios on a single SoC to reduce cost, form factor and external BOM. These devices require ubiquitous wireless connectivity, which means concurrent operation with different radios. While concurrent operation of multiple radios brings excellent user experiences, there exist great challenges in dealing with radio co-existence in an SoC. For example, concurrent operation between WiFi and BT, both oper- ating in the 2.4GHz ISM band, sets additional requirements in RF front-end cir- cuits and system control. In addition, thermal effect of the integrated WiFi PA needs to be compensated to minimize its impact on the frequency-precise GPS system.

A fractional spur reduction technique for RF TDC-based all digital PLLs

In this paper, a technique is proposed to suppress the fractional spur induced by non-linearity of the loop in all digital PLLs (ADPLLs). The measurement results show that the fractional spurs are reduced by at least 9 dB, to below -75 dBc, when the technique is applied to a conventional all digital PLL (ADPLL) at 3.6 GHz. The extra silicon area needed for technique is only 0.02 mm2.

28.2 A 0.29mm 2 frequency synthesizer in 40nm CMOS with 0.19ps rms jitter and <-100dBc reference spur for 802.11ac

Conventional analog PLLs do not scale well with process when compared to all-digital PLLs due to several substantial building blocks such as the loop filter and charge pump (CP). To achieve the required phase noise, the in-band noise is typically suppressed by increasing CP current and loop filter size, while the out-of-band noise is reduced by improving VCO tank Q; both lead to increased die area. This paper presents a fractional-N synthesizer targeting the relatively stringent phase noise requirement to support 256-QAM and MIMO in 802.11ac. It deploys the following techniques to simultaneously address requirements of compact area, low noise and fast calibration: reuse of VCO inductor area for the loop filter; a PFD and CP design that relaxes CP design constraints without sacrificing noise; inductor-less LO generation for 802.11bgn mode; and an area-efficient reference clock doubler and associated calibration scheme. The synthesizer block diagram is shown in Fig. 28.2.1. In 802.11ac/a mode a frequency tripler followed by I/Q dividers realizes the 3/2 frequency multiplication and I/Q generation. In 802.11bgn mode, an LO generation circuit performs the 2/3 frequency multiplication and I/Q generation. This frequency plan features overlapping VCO tuning ranges between 802.11ac/a (FLO=4915~5825MHz) and 802.11bgn (FLO=2412~2484MHz) modes, such that the VCO designed for 802.11ac/a can support 802.11bgn without additional tuning range.

An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability

In this paper, an analog enhanced all digital fractional-N PLL is proposed. An analog feed-forward circuits replace the time-to-digital converter used in conventional all digital PLL (ADPLLs) to provide a linear phase modulation path which is insensitive to quantization error and non-linearity of digital controlled oscillator (DCO). Its advantages include 1) Eliminating fractional spurs and noise induced by quantization error and the latency induced by the digital circuits in ADPLLs 2) Relaxing both digital controlled oscillator (DCO) and analog feed-forward circuit design requirements. 3) Providing a linear phase modulation path which can be self calibrated by using the digital loop filter. 4) Reducing loop filter area by using digital loop filter. The fractional spurs are 9 to 30 dB lower than the latest reported ADPLLs. At 3.6 GHz under fractional-N mode operation, the fractional spur is under -75 dBc, the phase noise is -115.6 dBc/Hz @400 KHz, -134.9 dBc/Hz @3 MHz. The performance satisfies GSM/GPRS/EDGE system requirements.