Shu-Hung Chou

A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS

The proliferation of location-based applications inside various handheld electronic devices, such as mobile phones and internet tablets, demands the GPS system to have low power consumption, small form-factor and be co-located on the same device with other radio systems, such as cellular, BT, and WLAN. The conventional GPS solution often uses two SAW filters, before and after an external LNA, to meet the requirements of low noise and multi-radio coexistence. Nevertheless, it is highly desirable to remove the external LNA and interstage SAW filter due to size and cost, which presents a great design challenge to achieve high out-of-band linearity with very low power consumption. To fulfill these stringent requirements, a more comprehensive approach is needed to target a radio architecture with a proper RX system budgeting and optimal circuit design. In addition, a GPS system can be desensitized by unexpected in-band blockers generated from other subsystems on the same platform, such as LCD display, PMU, CPU system clocks, etc. The GPS digital baseband processor must possess the capability to withstand in-band blockers without significant performance degradation. This paper presents a GPS/Galileo SoC with an adaptive in-band blocker cancellation scheme, which is implemented in a 65nm CMOS process.

A 110nm RFCMOS GPS SoC with 34mW −165dBm tracking sensitivity

A high performance RFCMOS SoC GPS navigation solution is introduced. It supports various location and navigation applications, including autonomous GPS, SBAS, DGPS (RTCM), and AGPS in L1-band at 1575.42MHz. A wide range of reference frequencies are supported to comply with other handheld specifications. The base-band architecture is optimized for the correlation efficiency and the power consumption of one single correlating operation. Hence this SoC receiver achieves the industrys highest levels of sensitivity, accuracy, and Time-to-First-Fix (TTFF) with the lowest power consumption. PMIC is also integrated in the SoC, no external LDO and power switching circuit is needed for all voltage domains, including RTC.

Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHY

Multi-format CD/DVD SoC, integrating an RF/AFE and a 1.5 Gb/s SATA PHY, is presented. It supports a 471Mb/s 18times DVD. A partial parity mode reduces SDRAM bandwidth and a power control mode minimizes the system clock rate. The 0.18mum CMOS SoC has 10M transistors, occupies 5.4 times 5.1mm2, and consumes 772mW during a 16times DVD read

A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications

A SoC, integrating RF/AFE and 1.5 Gb/s SATA PHY, is presented. It supports 471 Mb/s bit-rate at 18timesS DVD. A partial parity mode reduces SDRAM bandwidth. A power control mode minimizes system clock rate. The SoC has 10M transistors, occupies 5.4 times 5.1 mm2 in 0.18 mm CMOS process, and consumes 772 mW during 16timesS DVD read