Biyao Zhao

On finding the optimal number of decoupling capacitors by minimizing the equivalent inductance of the PCB PDN

PCB-PDN design remains a challenge with the reducing noise margins. One aspect of PDN design is finding the number of decoupling capacitors required for each power rail. As more capacitors are added, the mid frequency equivalent inductance in the impedance of the PCB-PDN converges to a minimum value for each placement pattern. This convergence is studied for different placement patterns to find the least number of capacitors required to satisfy a certain convergence criteria. A first principle method is used resonant cavity model for the analysis.

Analytical PDN voltage ripple calculation using simplified equivalent circuit model of PCB PDN

Printed circuit board (PCB) power distribution network (PDN) design performance depends on the peak voltage ripple caused by the integrated circuit (IC) switching currents. The input impedance seen by the IC looking into the PCB PDN can be calculated using a physics-based circuit model extracted from the cavity model approach. The input impedance is fitted to a simplified circuit model used to represent the PCB PDN. Using a switching current profile, the frequency domain noise voltage is found and transformed to the time domain ripple waveform which can then be used to evaluate the PDN design performance.

Effect of narrow power fills on PCB PDN noise

The printed circuit board (PCB) power delivery network (PDN) performance has become critical with the reducing margins on power noise. This paper deals with a specific question about the size of the power area fill used to route the power current from the dc regulator to integrated circuit(IC), and also used for connecting to the decoupling capacitors. With increased PCB real estate costs, narrow power fills are required, which results in an increase in the connection inductance of decoupling capacitors. This paper uses a proven lumped circuit model extraction procedure, based on the first principle resonant cavity model, to demonstrate the effect of narrow and wide area fills used in typical PCB PDN designs. The frequency domain results thus obtained are used with typical IC current draw profiles to show the impact on the noise voltage developed at the IC. Some design guidelines and conclusions are drawn from these results.

Modeling and analysis of package PDN for computing system based on cavity model

Recent computing systems consume more than several hundred watts of power and a robust PDN design is critical to minimize power/ground (P/G) voltage fluctuation and get stable performance. In most cases, the IC package (PKG) PDN determines mid-frequency P/G noise characteristics. The PDN of our target IC package consists of more than ten thousands staggered microvias and tens of layers, representing a significant modeling challenge. Commercial tools can estimate the PKG PDN impedance via full-wave simulations, but it has several limitations at pre-layout stage. Whole simulation should be run for every small geometry changes and it takes much time. It can give circuit model seen at port, but does not provide physics-based circuit models corresponding to whole current path. In this paper we apply the cavity model, which has been previously largely used for PCB modeling, to a complex organic package structure. We here describe the assumptions used to get an equivalent circuit model for this type of geometry and the comparison of its loop inductances with commercial tools. The cavity model gives about 10 % error compared to commercial tool and the reason of error is analyzed. In addition, a study of the PKG decoupling capacitors location is performed with the goal of a minimal loop inductance. In the final paragraph, several unique features of the PKG PDN compared to PCB PDN modeling are described.

Cavity model method based with gradient current distribution along the via for power integrity simulation

Cavity model is one of the key computational models for power distribution network simulation. However, the conventional cavity model assumes uniform current distribution along the via and its accuracy is limited to the coupling of close-placed vias. This paper presents an improved cavity model based with gradient current distribution assumption. The loop inductance and surface current distribution are simulated by the proposed cavity model. The comparison between improved and original models is employed to demonstrate the advantage of proposed model.

A novel z-directed embedded component for the reduction of voltage ripple on the power distribution network for PCBs

A new capacitor package and PCB embedding technique is introduced to significantly reduce the system power distribution network impedance at the pads of surface mounted integrated circuits. The capacitor is multi-layer ceramic capacitor (MLCC) that is a right cylindrical shape with via channels in the outer wall along the axis of the part. The capacitor called a Z-Directed component (ZDC) is then pressed into a hole in the PCB. The connections to the component are then made by the copper plating process similar to via hole construction. This new configuration dramatically improves the PDN performance of PCBs with fewer components than the conventional solution with SMD decoupling capacitors.

A novel Z-directed embedded component for the reduction of voltage ripple on the power distribution network for PCBs

A new capacitor package and PCB embedding technique is introduced to significantly reduce the system power distribution network impedance at the pads of surface mounted integrated circuits. The capacitor is multi-layer ceramic capacitor (MLCC) that is a right cylindrical shape with via channels in the outer wall along the axis of the part. The capacitor called a Z-Directed component (ZDC) is then pressed into a hole in the PCB. The connections to the component are then made by the copper plating process similar to via hole construction. This new configuration dramatically improves the PDN performance of PCBs with fewer components than the conventional solution with SMD decoupling capacitors.

Transient simulation for power integrity using physics based circuit modeling

A transient simulation analysis is proposed for printed circuit board (PCB) power distribution network (PDN) by using physics based circuit model. The PCB PDN is divided into different blocks. Different modeling methods are used to provide physics-based circuit models for each block. Then, Hspice simulation is used to do transient simulation for the PCB PDN based on the circuit.

Inductance extraction for physics-based modeling of power net area fills with complex shapes and voids using the plane-pair PEEC method

Identifying the dominant inductance in power distribution network design for multi-layer printed circuit boards that use power net area fills is essential. The plane-Pair partial element equivalent circuit method is used herein to extract a lumped inductance suitable for a physics-based circuit model for power net area fills. The method is being applied for evaluating inductance for irregular geometry with cutouts and holes.

Surface current distribution for PCB PDNGeometry

Surface current distribution provides an intuitive perspective on how the current flows, which is critical for high speed design. The surface current distribution for the power distribution network (PDN) in printed circuit board (PCB) is related to the input impedance observed by the IC looking into the PCB PDN. Two different principle methods are used to describe the current distribution, namely plane-pair PEEC (PPP) and resonant cavity model.