Brice Achkir

Modeling and Application of Multi-Port TSV Networks in 3-D IC

Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for 3-D integrated circuits (ICs). While arrays of TSVs are needed in 3-D IC, there only exists a frequency-dependent resistance, inductance, conductance and capacitance circuit model for a pair of TSVs with coupling between them. In this paper, we develop a simple yet accurate circuit model for a multiport TSV network (e.g., coupled TSV array) by decomposing the network into a number of TSV pairs and then applying circuit models for each of them. We call the new model a pair-based model for the multiport TSV network. It is first verified against a commercial electromagnetic solver for up to 20 GHz and subsequently employed for a variety of examples for signal and power integrity analysis.

Analytical expressions for transfer function of supply voltage fluctuation to jitter at a single-ended buffer

In this paper, the transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions. The expressions for the jitter transfer function is validated by comparison with HSPICE simulation, and applied to an example for statistical jitter estimation.

Analytical Transfer Functions Relating Power and Ground Voltage Fluctuations to Jitter at a Single-Ended Full-Swing Buffer

The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer. The analytic transfer functions are derived from a linear differential equation obtained from asymptotic linear inverter I-V curves. The transfer functions are validated by comparison with HSPICE simulations. The estimated jitter is compared with the simulated jitter using eye diagrams with single-frequency and multitone supply voltage fluctuations.

Optimization of power delivery network design for multiple supply voltages

Great power demands and low-power techniques have increased the requirements on the power delivery network, especially with multiple supply voltages. In this paper, methods for optimizing decoupling capacitor allocation and placement for multiple power nets are presented. Based on a physics-based circuit model extraction for the PCB-PDN structures, a two-level optimization procedure is proposed. First, stackup and potential locations and patterns for power and ground vias are optimized based on design guidelines. In the second step, distribution and allocation of decoupling capacitors are optimized targeting for the system-level PDN performance among multiple supply voltages by an integer linear programming (ILP) algorithm. The physical properties of the decoupling capacitors are described as circuit elements in the equivalent circuit model. Thus, instead of full-wave analysis, only efficient circuit simulations are needed in the optimization process. The proposed optimization methods are applied in a complex system including integrated circuit with multiple supply voltages. Compared to the original unoptimized design, the optimized PDN impedance for the worst designed power nets improved 400% with the same cost of decoupling.

Material parameter extraction using Time-Domain TRL (t-TRL) measurements

Characterizing materials used in Printed Circuit Board (PCB) manufacturing is becoming increasingly important in link path analysis as the data rates are increasing. The material properties governing the performance of the signal passing through a transmission line are frequency-dependent. Using frequency-domain vector network analyzer (VNA) measurements and Through-Reflect-Line (TRL) calibration, these parameters can be determined accurately. But a Time-Domain Reflectometer (TDR) provides a relatively inexpensive and simple way of characterizing transmission lines, and it is easily accessible to Signal Integrity engineers. With the time-domain TRL (t-TRL) calibration technique [1], it is now possible to de-embed such discontinuities as connectors, cables, etc., in the path of the transmission line using time-domain measurements. From the calibrated results, material properties can be extracted in the same way as it is done in the frequency domain. This paper describes a t-TRL technique to obtain accurate frequency domain S-parameters from time domain measurements. The calibrated results are converted into the ABCD parameters. The propagation constant is obtained through the ABCD parameters, from which attenuation loss and phase constant are extracted. Dielectric constant is extracted from the phase constant and the total attenuation constant. Curve-fitting technique is used to split the losses into conductor and dielectric loss. Once dielectric loss is determined, loss tangent can be calculated. The results are compared for three test vehicles, and are also compared with frequency domain VNA measurements. The results from the t-TRL calibration technique are also compared with another known extraction procedure.

Fast admittance computation for TSV arrays

A fast method to calculate the admittance matrix of Through Silicon Vias (TSVs) is proposed in this paper. The silicon dioxide layers are equivalently modelled using the bound charge on the conductor surfaces as well as on the dielectric interface between the silicon dioxide and the silicon regions. Unknown surface densities of both the free and bound charge are expanded using the axial harmonics. Galerkins method is then applied to obtain the capacitance and conductance matrices. The proposed method is validated with a full-wave 2D cross-sectional analysis tool for a typical TSV pair structure. Comparisons with popular closed-form expressions are also discussed.

Analytical PDN voltage ripple calculation using simplified equivalent circuit model of PCB PDN

Printed circuit board (PCB) power distribution network (PDN) design performance depends on the peak voltage ripple caused by the integrated circuit (IC) switching currents. The input impedance seen by the IC looking into the PCB PDN can be calculated using a physics-based circuit model extracted from the cavity model approach. The input impedance is fitted to a simplified circuit model used to represent the PCB PDN. Using a switching current profile, the frequency domain noise voltage is found and transformed to the time domain ripple waveform which can then be used to evaluate the PDN design performance.

Formulation and Network Model Reduction for Analysis of the Power Distribution Network in a Production-Level Multilayered Printed Circuit Board

A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias.

On-chip voltage regulator module (VRM) effect on power/ground noise and jitter at high-speed output buffer

On-chip voltage regulator module (VRM) for the reduction of power/ground noise on power distribution network (PDN) and jitter minimization at high-speed output buffer is introduced. The basic topology and optimized operation for on-chip VRM is analyzed. A PDN with on-chip VRM shows reduced power/ground noise through removing additional effects coming from package/PCB PDN. Also, when on-chip VRM is implemented on PDN of high-speed output buffers, jitter at output signal is lower. Improvements on PDN and jitter through on-chip VRM are shown and validated with SPICE simulation with 110nm CMOS technology library.

Comparative study of transmission lines design for 2.5D silicon interposer

In this paper, we present the results of a comparative study performed on six commonly used on-chip differential trace designs in newly emerging 2.5D silicon interposer with high-speed signalling. A generic equivalent circuit model is proposed based on physical geometry. The circuit model is compatible for all the trace structures studied. Impacts of circuit elements in the model are explained theoretically with a physics-based design optimization method. Tradeoff between channel performance and I/O numbers for various trace designs are also discussed in the paper. Unequalized eye of a 10Gb/s simulated transmitter with the best selected on-chip transmission lines geometries showing the possibility to achieve successful communication for 10 Gb/s signal through 40-mm interconnects on the silicon interposer.