Bo-Jr Huang

Design and Analysis for a 60-GHz Low-Noise Amplifier With RF ESD Protection

An RF electrostatic discharge (ESD) protection for millimeter-wave (MMW) regime applied to a 60-GHz low-noise amplifier (LNA) in mixed-signal and RF purpose 0.13-mum CMOS technology is demonstrated in this paper. The measured results show that this chip achieves a small signal gain of 20.4 dB and a noise figure (NF) of 8.7 dB at 60 GHz with 65-mW dc power consumption. Without ESD protection, the LNA exhibits a gain of 20.2 dB and an NF of 7.2 dB at 60 GHz. This ESD protection using an impedance isolation method to minimize the RF performance degradation sustains 6.5-kV voltage level of the human body model on the diode and 1.5 kV on the core circuit, which is much higher than that without ESD protection (< 350 V). To our knowledge, this is the first CMOS LNA with RF ESD protection in the MMW regime and has the highest operation frequency reported to date.

Millimeter-Wave Low Power and Miniature CMOS Multicascode Low-Noise Amplifiers with Noise Reduction Topology

In this paper, the design and analysis of CMOS multicascode configuration with noise reduction topology are proposed. Two low power and miniature low-noise amplifiers (LNAs) were designed and fabricated for demonstration. One with cascode device was designed at V -band in 65-nm process, and the other with triple-cascode structure was fabricated at Q -band in 0.13-¿ m technology. To minimize the noise figure and maximize the small-signal gain, inductors are designed and placed between transistors of the cascode and triple-cascode configurations. Based on this approach, the Q-band LNA has a gain of 14.3 dB and a noise figure of 3.8 dB at 38 GHz, with a power consumption of 28.8 mW. The V-band LNA presents a gain of 14.4 dB and a noise figure of 4.5 dB at 54.5 GHz, with a power consumption of 10 mW. The chip size of the V- and Q-band LNAs are 0.55 × 0.45 mm2 and 0.42 × 0.6 mm2, including all the testing pads. Compared with the conventional cascode LNAs, the proposed cascode LNA shows better noise figure and lower power consumption whereas the triple-cascode LNA features higher gain performance.

A 2–40 GHz Active Balun Using 0.13

A 2 to 40 GHz broadband active balun using 0.13 mum CMOS technology is presented in this letter. Using two-stage differential amplified pairs, the active balun can achieve a wideband performance with the gain compensation technique. This active balun exhibits a measured small signal gain of 0 plusmn1, with the amplitude imbalances below 0.5 dB and the phase differences of 180 plusmn10deg from 2 to 40 GHz. The core active balun has a low power consumption of 40 mW, and a compact area of 0.8 mm x 0.7 mm. This proposed balun achieved the highest operation frequency, the widest bandwidth, and the smallest size among all the reported active baluns.

\mu{\rm m}

This paper proposes a new ring-based triple-push voltage-controlled oscillator (VCO) architecture to achieve a wide tuning range and high operating frequencies. Two ring-based triple-push VCOs, one with a continuous frequency tuning range of 0.2-34 GHz, fabricated in 0.13- mum CMOS, and the other with a range of 0.1-65.8 GHz, fabricated in 90-nm CMOS, are presented in this paper. These two VCOs demonstrate that the proposed VCO architecture can achieve a very wide continuous tuning range, up to millimeter-wave frequencies, without any device-switching operations. In addition to the wide tuning range, the chip area of the proposed VCO is very small, allowing integration into a phase-locked loop. The power consumptions of the 0.2-34- and 0.1-65.8-GHz VCOs are 2-70 mW from a 2-V supply voltage, and 1.2-26.4 mW from a 1.2-V supply voltage, respectively. The fundamental and second harmonic rejections are better than 15 dB for both VCOs.

CMOS Process

10-35 GHz doubly balanced mixer using a 0.13-mum CMOS foundry process is presented in this letter. Using the bulk-driven topology, the number of transistors of the doubly balanced mixer is reduced; thus the mixer can achieve a low supply voltage and low power consumption. This bulk-driven mixer exhibits a measured conversion gain of -1 plusmn 2 dB from 10 to 35 GHz of radio frequency (RF) with a fixed intermediate frequency (IF) of 100 MHz. The measured local oscillation (LO) to IF and RF-IF isolations are better than 30 dB. The chip area of the mixer is 0.6 times 0.4 mm2. The total power consumption included output buffer is only 6 mW.

Ring-Based Triple-Push VCOs With Wide Continuous Tuning Ranges

In this paper, a frequency doubler is developed for MMW applications in a GaAs 2-mum HBT process. This balanced doubler adopts the cascode devices to achieve a high conversion gain, with a built-in 180deg reduced-size Marchand balun for fundamental suppression. In addition, because HBT presents a high beta factor (current gain), an on-chip stable voltage source is desired to maintain the collector current in the doubler. Thus, a transistor biased in the saturation region can be used to fix the base voltage and sustains the doubler in the pinch-off region. Under 5-dBm input drive, this balanced doubler demonstrates a measured conversion gain of 6.1 dB at 31 GHz. The fundamental rejection is better than 23 dB.

A 10–35 GHz Low Power Bulk-DrivenMixer Using 0.13

A miniature 40- to 76-GHz monolithic balanced distributed frequency doubler is developed in a commercial 0.13-mum CMOS process. This balanced doubler consists of a reduced-size broadside-coupled Marchand balun and two distributed doublers, and suppresses fundamental signals better than 25 dB. The measured conversion losses are 8-11 dB for the output frequencies from 40 to 76-GHz under 6-dBm input drive, with a low dc power consumption of 12 mW. The chip size is 0.64 times 0.65 mm2. To the best of our knowledge, this doubler achieves the widest bandwidth among all the CMOS doublers reported to date.

\mu

In this paper, the design and analysis of two novel high robustness RF electrostatic discharge (ESD) protection are proposed in GaAs 2-μm HBT process. One incorporates with the ESD devices to form a bandpass filter structure with good impedance matching, which has eight discharging paths. The other is fabricated with parasitic capacitance reduction technique for the ESD protection, and has four discharging paths. These two protection circuits are also applied to 5.8-GHz amplifiers for demonstration. In the meanwhile, two amplifiers without ESD protection and with conventional ESD protection are fabricated in parallel for comparison. Based on the measurement results, it indicates that the two proposed ESD-protected amplifiers feature much higher ESD robustness and better RF performance than the conventional design.

m CMOS Process

A novel ring-based triple-push voltage-controlled oscillator (VCO) with a continuous range from 0.2 to 34 GHz is proposed and realized using a commercial 0.13-μm 1P8M CMOS process. The output power of the VCO is −18 dBm with only ±2 dB variation in the full band. The fundamental rejection is more than 15 dB, and the second harmonic rejection is more than 25 dB. This VCO achieves the widest continuous tuning range reported to date.