Kun-You Lin
National Taiwan University
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Publication
Featured researches published by Kun-You Lin.
IEEE Transactions on Microwave Theory and Techniques | 2006
Mei-Chao Yeh; Zuo-Min Tsai; Ren-Chieh Liu; Kun-You Lin; Ying-Tang Chang; Huei Wang
A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.
IEEE Microwave and Wireless Components Letters | 2005
Shih-Chieh Shin; Ming-Da Tsai; Ren-Chieh Liu; Kun-You Lin; Huei Wang
A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-/spl mu/m CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum noise figure of 3.9 dB at 24.3 GHz. The supply voltage and supply current are 1 V and 14 mA, respectively. To the authors knowledge, this LNA demonstrates the lowest noise figure among the reported LNAs in standard CMOS processes above 20 GHz.
IEEE Transactions on Microwave Theory and Techniques | 2012
Jing-Lin Kuo; Yi-Fong Lu; Ting-Yi Huang; Yi-Long Chang; Yi-Keng Hsieh; Pen-Jui Peng; I-Chih Chang; Tzung-Chuen Tsai; Kun-Yao Kao; Wei-Yuan Hsiung; J. Wang; Y. A. Hsu; Kun-You Lin; Hsin-Chia Lu; Yi-Cheng Lin; Liang-Hung Lu; Tian Wei Huang; Ruey-Beei Wu; Huei Wang
AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 × 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm2 in the TX integrated circuit (IC) and 4.18 mm2 in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern.
international solid-state circuits conference | 2007
Chi-Hsueh Wang; Hong-Yeh Chang; Pei-Si Wu; Kun-You Lin; Tian Wei Huang; Huei Wang; Chun Hsiung Chen
A 60GHz six-port transceiver IC in a standard-bulk 0.13mum CMOS process is reported. This chip is composed of a VCO, a modified reflection-type I/Q modulator, a buffer amplifier, an SPDT switch, an LNA, and a six-port detector. The measured results show 4.5dB conversion gain and 4Gb/s modulation BW with 97.7mW DC power consumption.
IEEE Transactions on Microwave Theory and Techniques | 2004
Kun-You Lin; Wen-Hua Tu; Ping-Yu Chen; Hong-Yeh Chang; Huei Wang; Ruey-Beei Wu
This paper describes the design of millimeter-wave wide-band monolithic GaAs passive high electron-mobility transistor (HEMT) switches using the traveling-wave concept. This type of switch combined the off-state shunt transistors and series microstrip lines to form an artificial transmission line with 50-/spl Omega/ characteristic impedance. A 15-80-GHz single-pole double-throw (SPDT) switch in conjunction with quarter-wavelength impedance transformers demonstrates an insertion loss of less than 3.6 dB and an isolation of better than 25 dB. Another type of wide-band switch was designed by using a series HEMT switch to replace the quarter-wavelength transformer, and the operating band can be extended to dc. With this scheme, dc-80-GHz single-pole single-throw (SPST) and dc-60-GHz SPDT switches are also developed with compact chip size. From dc to 80 GHz, the insertion loss and isolation of the SPST switch are better than 3 and 24 dB, respectively. The SPDT switch has an insertion loss of better than 3 dB and an isolation of better than 25 dB from dc to 60 GHz. The analysis of circuit characteristics and design procedures are also included. It is concluded that the device periphery can be selected for the desired bandwidth, while the number of transistors is decided to achieve the isolation.
IEEE Transactions on Microwave Theory and Techniques | 2007
Chin-Shen Lin; Pei-Si Wu; Mei-Chao Yeh; Jia-Shiang Fu; Hong-Yeh Chang; Kun-You Lin; Huei Wang
The analysis and systematic design procedure for multiconductor coupled-line Marchand baluns are presented in this paper. A simple two-conductor coupled-line model is used to analyze the Marchand balun and simplify the analysis significantly. Two monolithic balanced frequency doublers with miniature Marchand baluns are implemented to verify the design procedure. Both the chips achieve the smallest chip sizes at their operating frequencies with comparable performance.
IEEE Transactions on Microwave Theory and Techniques | 2009
Bo-Jr Huang; Chi-Hsueh Wang; Chung-Chun Chen; Ming-Fong Lei; Pin-Cheng Huang; Kun-You Lin; Huei Wang
An RF electrostatic discharge (ESD) protection for millimeter-wave (MMW) regime applied to a 60-GHz low-noise amplifier (LNA) in mixed-signal and RF purpose 0.13-mum CMOS technology is demonstrated in this paper. The measured results show that this chip achieves a small signal gain of 20.4 dB and a noise figure (NF) of 8.7 dB at 60 GHz with 65-mW dc power consumption. Without ESD protection, the LNA exhibits a gain of 20.2 dB and an NF of 7.2 dB at 60 GHz. This ESD protection using an impedance isolation method to minimize the RF performance degradation sustains 6.5-kV voltage level of the human body model on the diode and 1.5 kV on the core circuit, which is much higher than that without ESD protection (< 350 V). To our knowledge, this is the first CMOS LNA with RF ESD protection in the MMW regime and has the highest operation frequency reported to date.
IEEE Transactions on Microwave Theory and Techniques | 2009
Bo-Jr Huang; Kun-You Lin; Huei Wang
In this paper, the design and analysis of CMOS multicascode configuration with noise reduction topology are proposed. Two low power and miniature low-noise amplifiers (LNAs) were designed and fabricated for demonstration. One with cascode device was designed at V -band in 65-nm process, and the other with triple-cascode structure was fabricated at Q -band in 0.13-¿ m technology. To minimize the noise figure and maximize the small-signal gain, inductors are designed and placed between transistors of the cascode and triple-cascode configurations. Based on this approach, the Q-band LNA has a gain of 14.3 dB and a noise figure of 3.8 dB at 38 GHz, with a power consumption of 28.8 mW. The V-band LNA presents a gain of 14.4 dB and a noise figure of 4.5 dB at 54.5 GHz, with a power consumption of 10 mW. The chip size of the V- and Q-band LNAs are 0.55 × 0.45 mm2 and 0.42 × 0.6 mm2, including all the testing pads. Compared with the conventional cascode LNAs, the proposed cascode LNA shows better noise figure and lower power consumption whereas the triple-cascode LNA features higher gain performance.
IEEE Microwave and Wireless Components Letters | 2009
Jing-Lin Kuo; Zuo-Min Tsai; Kun-You Lin; Huei Wang
A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P<sub>sat</sub> of 13.8 dBm, P<sub>1</sub> <sub>dB</sub> of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V<sub>DD</sub> biased at 1.8 V. When V<sub>DD</sub> is biased at 3 V, it exhibits P<sub>sat</sub> of 18 dBm, P<sub>1</sub> <sub>dB</sub> of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm<sup>2</sup>. To the authors knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.
IEEE Transactions on Microwave Theory and Techniques | 2006
Kuo-Jung Sun; Zuo-Min Tsai; Kun-You Lin; Huei Wang
A noise optimization formulation for a CMOS low-noise amplifier (LNA) with on-chip low-Q inductors is presented, which incorporates the series resistances of the on-chip low-Q inductors into the noise optimization procedure explicitly. A 10-GHz LNA is designed and implemented in a standard mixed-signal/RF bulk 0.18-/spl mu/m CMOS technology based on this formulation. The measurement results, with a power gain of 11.25 dB and a noise figure (NF) of 2.9 dB, show the lowest NF among the LNAs using bulk 0.18-/spl mu/m CMOS at this frequency.