Bo-Tak Lim

64Mb mobile stacked single-crystal Si SRAM (S/sup 3/RAM) with selective dual pumping scheme (SDPS) and multi cell burn-in scheme (MCBS) for high density and low power SRAM

A 64Mb Mobile S/sup 3/RAM was designed with stacked single-crystal thin film transistor (SSTFT) cell using 80nm SRAM technology to overcome chip size penalty of conventional 6T-SRAM with improved performance. For 1.3V operation, word line (WL) and cell Vcc were pumped simultaneously using selective dual pumping scheme (SDPS). Access time of 49.2ns was achieved at 1.3V supply voltage. Multi cell burn-in scheme (MCBS) and standby current (ISB1) repair scheme enhanced the yield for the high density products.

Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM

A PRAM includes 8 b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled by processor-based built-in self-optimizer (BISO). A 4 Mb test PRAM is fabricated in a 90 nm 3-metal diode-switch PRAM cell technology. Measured margin increases by up to 221%.

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

With the growth of wearable devices, such as smart watches and smart glasses, there is an increasing demand for lower power dissipation, to achieve longer battery life with limited battery capacity. Nevertheless, memory bandwidth needs to increase to support high-resolution graphic engines. Since most wearable devices are event driven, they consume a bulk of power in standby mode. Therefore, it is crictical to reduce standby-mode power, as well as improve active-mode power efficiency. However, DRAMs periodic self-refresh, critical for data retention, imposes a lower bound on standby-mode power. This paper presents a 2Gb LPDDR4 SDRAM with 0.15mW standby mode power, which is 66% lower than the standby power for a memory of the same density. The proposed memory also achieves a bandwidth of 3.733Gb/s/pin. To extremely reduce standby mode power, an in-DRAM error-correction-code (ECC) engine is used for self-refresh current reduction. Intensive power gating in deep-power-down (DPD) mode, a temperature controlled internal power generator and an aggressively increased gate length is also used to reduce leakage current. In addition, active-mode power efficiency is improved by using a dual-page-size scheme.