Gong-Heum Han

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard. In this paper, we present a power-efficient LPDDR4 SDRAM operating at 3.2Gb/s/pin. Our LPDDR4 DRAM offers 2× bandwidth with improved power efficiency over LPDDR3 SDRAMs, due to the 2-channel architecture and low-voltage-swing terminated logic (LVSTL) [1]. Moreover, the supply voltage is further reduced to 1.0V in this work, 0.1V lower than the LPDDR4 standard, for extra power saving.

64Mb mobile stacked single-crystal Si SRAM (S/sup 3/RAM) with selective dual pumping scheme (SDPS) and multi cell burn-in scheme (MCBS) for high density and low power SRAM

A 64Mb Mobile S/sup 3/RAM was designed with stacked single-crystal thin film transistor (SSTFT) cell using 80nm SRAM technology to overcome chip size penalty of conventional 6T-SRAM with improved performance. For 1.3V operation, word line (WL) and cell Vcc were pumped simultaneously using selective dual pumping scheme (SDPS). Access time of 49.2ns was achieved at 1.3V supply voltage. Multi cell burn-in scheme (MCBS) and standby current (ISB1) repair scheme enhanced the yield for the high density products.

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

With the growth of wearable devices, such as smart watches and smart glasses, there is an increasing demand for lower power dissipation, to achieve longer battery life with limited battery capacity. Nevertheless, memory bandwidth needs to increase to support high-resolution graphic engines. Since most wearable devices are event driven, they consume a bulk of power in standby mode. Therefore, it is crictical to reduce standby-mode power, as well as improve active-mode power efficiency. However, DRAMs periodic self-refresh, critical for data retention, imposes a lower bound on standby-mode power. This paper presents a 2Gb LPDDR4 SDRAM with 0.15mW standby mode power, which is 66% lower than the standby power for a memory of the same density. The proposed memory also achieves a bandwidth of 3.733Gb/s/pin. To extremely reduce standby mode power, an in-DRAM error-correction-code (ECC) engine is used for self-refresh current reduction. Intensive power gating in deep-power-down (DPD) mode, a temperature controlled internal power generator and an aggressively increased gate length is also used to reduce leakage current. In addition, active-mode power efficiency is improved by using a dual-page-size scheme.